PL133-67 PhaseLink Corp., PL133-67 Datasheet - Page 4

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PL133-67

Manufacturer Part Number
PL133-67
Description
Low-power 2.25v To 3.63v Dc To 150mhz 1 6 Fanout Buffer Ic
Manufacturer
PhaseLink Corp.
Datasheet
SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature Devices)
Notes:
1. REF input has a threshold voltage of V
2. Parameter is guaranteed by design and characterization. Not 100% tested in produ ction.
3. All parameters are specified with loaded outputs .
NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices)
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
Parameter
t
t
t
t
Parameter
3
4
5
6
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
Duty Cycle
Rise Time
Fall Time
Output to Output Skew
Propagation Delay, REF Rising
Edge to CLKX Rising Edge
Additive Phase Jitter
Description
Description
-100
-110
-120
-130
-140
-150
-160
-60
-70
-80
-90
10
[2]
[2]
[2]
= t2 ÷ t1
VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical.
100
[2]
DD
[2]
/2
1000
PL133-67 Additive Phase Jitter:
Measured at 1.4V, Input is 50%
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
V
Offset=12KHz ~ 20MHz
Test Conditions
Test Conditions
DD
=3.3V, Frequency=100MHz
REF Input
2
10000
Offset Frequency (Hz)
PL133-67 Output
DD
/2
100000
www.phaselink.com
1000000
2
10000000
Min.
Min.
40
1
100000000
Rev 03/18/11
PL133-67
Typ.
Typ.
50
60
5
Max.
Max.
[3]
250
1.5
1.5
9.2
60
Page 4
Unit
Unit
ns
ns
ps
ns
%
fs

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