A54SX08-3VQ100I Actel, A54SX08-3VQ100I Datasheet - Page 34

• Manufacturer Part Number: A54SX08-3VQ100I
• Description: Semiconductors and Actives, Programmable Logic (FPGAs, PALs, CPLDs ...), fpga
• Manufacturer: Actel

Table 1-19 • A54SX16P Timing Characteristics (Continued)
1 -3 0
Parameter
TTL/PCI Output Module Timing
t
t
t
t
t
t
PCI Output Module Timing
t
t
t
t
t
t
TTL Output Module Timing
t
t
t
t
t
t
Note:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Delays based on 10 pF loading.
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
SX Family FPGAs
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
(Worst-Case Commercial Conditions, V
Description
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
3
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
CCR
Min.
RD1
'–3' Speed
= 4.75 V, V
+ t
v3.2
PDn,
Max.
1.5
1.9
2.3
1.5
2.7
2.9
1.8
1.7
0.8
1.2
1.0
1.1
2.1
2.0
2.5
3.0
2.3
2.9
or t
CCA
PD1
Min.
,V
'–2' Speed
+ t
CCI
RD1
= 3.0 V, T
Max.
+ t
1.7
3.1
2.0
1.1
2.5
2.7
2.2
2.6
1.7
3.3
2.0
1.0
1.2
1.3
2.3
2.9
3.5
3.3
SUD
, whichever is appropriate.
J
Min.
= 70°C)
'–1' Speed
Max.
2.0
2.4
3.0
1.9
3.5
3.7
2.3
2.2
1.1
1.5
1.3
1.5
2.8
2.6
3.2
3.9
3.1
3.7
Min.
'Std' Speed
Max.
2.3
2.9
3.5
2.3
4.1
4.4
2.7
2.6
1.3
1.8
1.5
1.7
3.3
3.1
3.8
4.6
3.6
4.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns