MC100LVEL56DWG ON Semiconductor, MC100LVEL56DWG Datasheet - Page 2

• Manufacturer Part Number: MC100LVEL56DWG
• Description: IC MULTIPLXR 2:1 DUAL ECL 20SOIC
• Manufacturer: ON Semiconductor
• Series: 100LVELr
• Type: Differential Digital Multiplexerr

Specifications of MC100LVEL56DWG

• Circuit: 2 x 2:1
• Independent Circuits: 1
• Voltage Supply Source: Dual Supply
• Voltage - Supply: 3 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: MC100L
• Number Of Lines (input / Output): 2.0 / 2.0
• Propagation Delay Time: 0.62 ns at 3.3 V
• Supply Voltage (max): - 3.8 V, + 3.8 V
• Supply Voltage (min): - 3 V, + 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 2.0
• Number Of Output Lines: 2.0
• Logic Type: Multiplexer
• No. Of Channels: 2
• Ratio: 2
• Supply Voltage Range: 3V To 3.8V
• Logic Case Style: SOIC
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Family Type: ECL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC100LVEL56DWGOS

Figure 1. 20−Lead Package (Top View) and Logic Diagram
Warning: All V
to Power Supply to guarantee proper operation.
V
D0a
20
CC
1
1
D0a
Q0
19
2
V
CC
Q0
18
BBO
3
1. For additional information, see Application Note AND8003/D.
and V
Table 3. ATTRIBUTES
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Moisture Sensitivity, (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
0
SEL0
D0b
17
4
EE
pins must be externally connected
D0b
16
5
SEL1
D1a
15
6
Characteristics
1
D1a
V
14
7
CC
Pb (Indefinite Time Out of Drypack)
V
Q1
13
BB1
8
0
http://onsemi.com
Q1
D1b
12
Charged Device Model
9
Human Body Model
V
D1b
10
11
EE
Machine Model
2
Pb−Free
* Pins will default LOW when left open.
Table 1. PIN DESCRIPTION
Table 2. TRUTH TABLE
SEL0
PIN
D0a* − D1a*
D0a* − D1a*
D0b* − D1b*
D0b* − D1b*
SEL0* − SEL1*
COM_SEL*
V
Q0 − Q1
Q0 − Q1
V
V
BB0
CC
EE
X
H
H
L
L
, V
UL 94 V−0 @ 0.125 in
BB1
SEL1
H
H
X
L
L
28 to 34
> 200 V
Level 1
Level 3
75 KW
> 2 kV
> 4 kV
Value
N/A
147
COM_SEL
ECL Common Select Input
FUNCTION
ECL Input Data a
ECL Input Data a Invert
ECL Input Data b
ECL Input Data b Invert
ECL Indiv. Select Input
Output Reference Voltage
ECL True Outputs
ECL Inverted Outputs
Positive Supply
Negative Supply
H
L
L
L
L
Q0,
Q0
a
b
b
a
a
Q1,
Q1
a
b
a
a
b