ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 232
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ATMEGA16-16AU SL602
Manufacturer Part Number
ATMEGA16-16AU SL602
Description
Manufacturer
Atmel
Datasheet
1.ATMEGA16-16AU_SL602.pdf
(357 pages)
- Current page: 232 of 357
- Download datasheet (8Mb)
Boundary-scan
Chain
Scanning the Digital
Port Pins
2466T–AVR–07/10
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
Off-chip connection.
Figure 116
cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a
bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –
ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are
not used in the following description.
The Boundary-scan logic is not included in the figures in the datasheet.
ple digital Port Pin as described in the section
details from
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-
ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in
scan chain read the actual pin value. For Analog function, there is a direct connection from the
external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-
tal logic and the analog circuitry.
Figure 116. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.
Pullup Enable (PUE)
Output Control (OC)
Output Data (OD)
Input Data (ID)
shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The
Figure 116
From Last Cell
0
1
replaces the dashed box in
0
1
0
1
0
1
ShiftDR
ClockDR
D
D
D
FF2
FF1
FF0
To Next Cell
Q
Q
Q
UpdateDR
“I/O Ports” on page
Figure
D
G
D
G
D
G
LD2
LD1
LD0
Q
Q
Q
117.
0
1
0
1
0
1
EXTEST
ATmega16(L)
50. The Boundary-scan
Figure 117
Figure 117
Vcc
Port Pin (PXn)
shows a sim-
to make the
232
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