IS62WV51216BLL-55TI-TR ISSI, IS62WV51216BLL-55TI-TR Datasheet

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IS62WV51216BLL-55TI-TR

Manufacturer Part Number
IS62WV51216BLL-55TI-TR
Description
Semiconductors and Actives, Memory
Manufacturer
ISSI
Datasheet
IS62WV51216ALL
IS62WV51216BLL
512K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns, 55ns
• CMOS low power operation
• TTL compatible interface levels
• Single power supply
• Fully static operation: no clock or refresh
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
02/24/05
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby
– 1.65V--2.2V V
– 2.5V--3.6V V
required
DD
DD
(62WV51216BLL)
(62WV51216ALL)
Lower Byte
Upper Byte
I/O8-I/O15
I/O0-I/O7
A0-A18
V
GND
DD
CS2
CS1
WE
OE
UB
LB
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
1-800-379-4774
DESCRIPTION
The
speed, 8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62WV51216ALL and IS62WV51216BLL are packaged
in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)
and 44-Pin TSOP (TYPE II).
ISSI
IS62WV51216ALL/ IS62WV51216BLL are high-
MEMORY ARRAY
COLUMN I/O
512K x 16
ISSI
's high-performance CMOS
ISSI
FEBRUARY 2005
®
1

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IS62WV51216BLL-55TI-TR Summary of contents

Page 1

... Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62WV51216ALL and IS62WV51216BLL are packaged in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm) and 44-Pin TSOP (TYPE II). A0-A18 ...

Page 2

... IS62WV51216ALL, IS62WV51216BLL PIN CONFIGURATIONS 48-Pin mini BGA (7.2mm x 8.7mm I I/O I GND A17 A7 I I/O GND A16 I/O I/O A14 A15 I/O NC A12 A13 15 H A18 A10 A8 A9 44-Pin TSOP (Type II ...

Page 3

... Read Write OPERATING RANGE ( Range Ambient Temperature IS62WV51216ALL (70ns) IS62WV51216BLL (55ns, 70ns) Commercial 0°C to +70°C Industrial –40°C to +85°C Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 02/24/ ...

Page 4

... IS62WV51216ALL, IS62WV51216BLL ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS V V Related to GND Storage Temperature STG P Power Dissipation T Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 5

... IS62WV51216ALL, IS62WV51216BLL (1) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level ...

Page 6

... IS62WV51216ALL, IS62WV51216BLL IS62WV51216ALL, POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I V Dynamic Operating Supply Current I I Operating Supply Current CS2 = V I TTL Standby Current (TTL Inputs) V CS1 = ULB Control V CS1 = V I CMOS Standby CS1 V ...

Page 7

... IS62WV51216ALL, IS62WV51216BLL IS62WV51216BLL, POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I V Dynamic Operating Supply Current I I Operating Supply Current CS2 = V I TTL Standby Current (TTL Inputs) V CS1 = ULB Control V CS1 = V I CMOS Standby CS1 V ...

Page 8

... IS62WV51216ALL, IS62WV51216BLL READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CS1/CS2 Access Time t t ACS1/ ACS2 OE Access Time t DOE OE to High-Z Output t (2) HZOE OE to Low-Z Output t (2) LZOE CS1/CS2 to High-Z Output ...

Page 9

... IS62WV51216ALL, IS62WV51216BLL AC WAVEFORMS (CS1, CS2, OE, AND UB/LB Controlled) READ CYCLE NO. 2 (1,3) ADDRESS OE CS1 s CS2 DOUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 10

... IS62WV51216ALL, IS62WV51216BLL WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time WC CS1/CS2 to Write End t t SCS1/ SCS2 t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width t (4) PWE ...

Page 11

... IS62WV51216ALL, IS62WV51216BLL WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CS1 CS2 WE LB, UB DOUT DIN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE CS1 CS2 WE LB, UB DOUT DIN Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 02/24/ ...

Page 12

... IS62WV51216ALL, IS62WV51216BLL WRITE CYCLE NO. 4 (UB/LB Controlled) ADDRESS OE LOW CS1 HIGH CS2 WE UB HZWE D OUT DATA UNDEFINED ADDRESS 1 ADDRESS PBW WORD 1 HIGH DATA IN VALID Integrated Silicon Solution, Inc. — www.issi.com — ISSI t WC ...

Page 13

... IS62WV51216ALL, IS62WV51216BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR DATA RETENTION WAVEFORM V DD 1.65V 1. CS1 GND DATA RETENTION WAVEFORM V DD 3.0 CE2 2. 0.4V GND Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 14

... IS62WV51216ALL, IS62WV51216BLL ORDERING INFORMATION IS62WV51216ALL (1.65V - 2.2V) Industrial Range: –40°C to +85°C Speed (ns) 70 ORDERING INFORMATION IS62WV51216BLL (2.5V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) 45 Industrial Range: –40°C to +85°C Speed (ns Order Part No. IS62WV51216ALL-70TI IS62WV51216ALL-70BI IS62WV51216ALL-70XI Order Part No. ...

Page 15

... IS62WV51216ALL, IS62WV51216BLL Mini Ball Grid Array Package Code: B (48-pin) Top View SEATING PLANE mBGA - 7.2mm x 8.7mm MILLIMETERS Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 A — — 1.20 — .24 — 0.30 0.009 A2 0.60 — — ...

Page 16

... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

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