P89LPC936FDH-S Philips, P89LPC936FDH-S Datasheet - Page 29
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P89LPC936FDH-S
Manufacturer Part Number
P89LPC936FDH-S
Description
ram, tssop, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, mcu, ic
Manufacturer
Philips
Datasheet
1.P89LPC936FDH-S.pdf
(75 pages)
- Current page: 29 of 75
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Philips Semiconductors
9397 750 15113
Product data sheet
Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources
(1) See
(2) P89LPC935/936
EAD (P89LPC933/934)
(RTCCON.1)
EADEE (P89LPC935)
WDOVF
Section 8.19 “CCU (P89LPC935/936)”
ERTC
RTCF
ENADCI0
ENADCI1
ADCI0
BNDI0
ENBI0
EEIF
ADCI1
BNDI1
ENBI1
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC933/934/935/936 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume
operation. Refer to
(2)
(2)
(2)
(2)
(2)
any CCU interrupt
EA (IE0.7)
TI & RI/RI
ES/ESR
EWDRT
ECCU
CMF2
CMF1
EKBI
ESPI
KBIF
EI2C
SPIF
EBO
BOF
EX0
EX1
EST
ET0
ET1
TF0
TF1
IE0
IE1
EC
(1)
TI
SI
Section 8.15 “Power reduction modes”
Rev. 06 — 20 June 2005
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC933/934/935/936
for details.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
002aab081
wake-up
(if in power-down)
interrupt
to CPU
29 of 75
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