ST72C334J4TAE STMicroelectronics, ST72C334J4TAE Datasheet - Page 132
ST72C334J4TAE
Manufacturer Part Number
ST72C334J4TAE
Description
8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces
Manufacturer
STMicroelectronics
Datasheet
1.ST72C334J4TAE.pdf
(150 pages)
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
15.9 CONTROL PIN CHARACTERISTICS
15.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Figure 89. Typical Application with RESET Pin
Notes:
1. Unless otherwise specified, typical data is based on T
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I
(I/O ports and control pins) must not exceed I
5. The R
scribed in
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
132/150
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
V
R
V
V
V
hys
OL
ON
IH
IL
EXTERNAL
CIRCUIT
IO
RESET
ON
USER
current sunk must always respect the absolute maximum rating specified in
Figure
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
(see
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
pull-up equivalent resistor is based on a resistive transistor (corresponding I
8)
Figure
90). This data is based on characterization results, not tested in production.
V
DD
91,
0.1µF
0.1µF
Parameter
Figure
V
DD
4.7kΩ
h(RSTL)in
2)
92)
7)
2)
4)
6)
can be ignored.
5)
VSS
3)
.
DD
V
V
External pin or
internal reset sources
, f
DD
IN
RESET
=
OSC
A
=5V
8)
V
=25°C and V
Conditions
SS
R
, and T
ON
I
I
V
V
IO
IO
V
DD
DD
DD
=+5mA
=+2mA
=5V
=3.4V
A
DD
unless otherwise specified.
=5V.
0.7xV
Min
20
80
20
DD
Section 15.2.2
ON
Typ
0.68
0.28
400
100
40
30
6
current characteristics de-
1)
INTERNAL
RESET CONTROL
WATCHDOG RESET
LVD RESET
0.3xV
and the sum of I
Max
0.95
0.45
120
100
60
DD
ST72XXX
1/f
Unit
SFOSC
mV
kΩ
µs
µs
ns
V
V
IO
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