FM24C64-GTR Ramtron, FM24C64-GTR Datasheet - Page 7

• Manufacturer Part Number: FM24C64-GTR
• Description: memory, soic, ram, Memory, Semiconductors and Actives, bit, serial
• Manufacturer: Ramtron

Endurance
Internally, a FRAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read or write cycle. The FRAM architecture
is based on an array of rows which are subdivided
into segments. Rows (defined by A12-A5) are
subdivided into 4 segments (A4-A3). Each access
causes an endurance cycle for a row segment. In the
FM24C64, there are 8 bytes (defined by A2-A0) per
Rev. 3.0
Mar. 2005
By FM24C64
By Master
By FM24C64
By Master
Start
S
DEVICE ADDRESS
Start
S
DEVICE ADDRESS
By FM24C64
0
Address
A
By Master
X X X
ADDRESS MSB
Acknowledge
Start
1
Figure 9. Selective (Random) Read
S
Address
Figure 7. Current Address Read
A
DEVICE ADDRESS
A
Figure 8. Sequential Read
Address
ADDRESS LSB
DATA BYTE
Acknowledge
Acknowledge
1
A S
A
Start
A
DEVICE ADDRESS
Data
segment. Endurance can be optimized by ensuring
frequently accessed data is located in different
segments. Regardless, FRAM read and write
endurance is effectively unlimited at the 1MHz two-
wire speed. Even at 3000 accesses per second to the
same segment, 10 years time will elapse before 1
trillion endurance cycles occur.
DATA BYTE
Acknowledge
DATA BYTE
Data
1
No Acknowledge
A
A
1
DATA BYTE
P
Stop
DATA BYTE
Acknowledge
Data
A
No Acknowledge
DATA BYTE
1 P
No Acknowledge
Stop
FM24C64
1 P
Stop
7 of 12