SST27SF020-70-3C-NH Silicon Storage Tech, SST27SF020-70-3C-NH Datasheet

SST27SF020-70-3C-NH

Manufacturer Part Number

SST27SF020-70-3C-NH

Description

256K x 8 M

Manufacturer

Silicon Storage Tech

Datasheet

1.SST27SF512903CPG.pdf (23 pages)

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512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8

• 4.5-5.5V Read Operation

• Superior Reliability

• Low Power Consumption

• Fast Read Access Time

PRODUCT DESCRIPTION

The SST27SF512/010/020 are a 64K x8 / 128K x8 / 256K

x8 CMOS, Many-Time Programmable (MTP) low cost

flash, manufactured with SST’s proprietary, high perfor-

mance SuperFlash technology. The split-gate cell design

and thick oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches.

These MTP devices can be electrically erased and pro-

grammed at least 1000 times using an external program-

mer with a 12V power supply. They have to be erased prior

to programming. These devices conform to JEDEC stan-

dard pinouts for byte-wide memories.

Featuring

SST27SF512/010/020 provide a Byte-Program time of 20

µs. Designed, manufactured, and tested for a wide spec-

trum of applications, these devices are offered with an

endurance of at least 1000 cycles. Data retention is rated at

greater than 100 years.

The SST27SF512/010/020 are suited for applications that

require infrequent writes and low power nonvolatile stor-

age. These devices will improve flexibility, efficiency, and

performance while matching the low cost in nonvolatile

applications that currently use UV-EPROMs, OTPs, and

mask ROMs.

To meet surface mount and conventional through hole

requirements, the SST27SF512 are offered in 32-lead

PLCC, 32-lead TSOP , and 28-pin PDIP packages. The

SST27SF010/020 are offered in 32-pin PDIP , 32-lead

PLCC, and 32-lead TSOP packages. See Figures 1, 2, and

3 for pin assignments.

S71152-11-000

– Endurance: At least 1000 Cycles

– Greater than 100 years Data Retention

– Active Current: 20 mA (typical)

– Standby Current: 10 µA (typical)

– 70 ns

high-performance

SST27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories

9/05

SST27SF512 / SST27SF010 / SST27SF020

Byte-Program,

the

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

• Fast Byte-Program Operation

• Electrical Erase Using Programmer

• TTL I/O Compatibility

• JEDEC Standard Byte-wide EPROM Pinouts

• Packages Available

• All non-Pb (lead-free) devices are RoHS compliant

Device Operation

The SST27SF512/010/020 are a low cost flash solution

that can be used to replace existing UV-EPROM, OTP,

and mask ROM sockets. These devices are functionally

(read and program) and pin compatible with industry

standard EPROM products. In addition to EPROM func-

tionality, these devices also support electrical Erase

operation via an external programmer. They do not

require a UV source to erase, and therefore the pack-

ages do not have a window.

Read

The Read operation of the SST27SF512/010/020 is con-

trolled by CE# and OE#. Both CE# and OE# have to be low

for the system to obtain data from the outputs. Once the

address is stable, the address access time is equal to the

delay from CE# to output (T

put after a delay of T

assuming that CE# pin has been low and the addresses

have been stable for at least T

high, the chip is deselected and a typical standby current of

10 µA is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high.

– Byte-Program Time: 20 µs (typical)

– Chip Program Time:

– Does not require UV source

– Chip-Erase Time: 100 ms (typical)

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 28-pin PDIP for SST27SF512

– 32-pin PDIP for SST27SF010/020

1.4 seconds (typical) for SST27SF512

2.8 seconds (typical) for SST27SF010

5.6 seconds (typical) for SST27SF020

These specifications are subject to change without notice.

MTP is a trademark of Silicon Storage Technology, Inc.

from the falling edge of OE#,

). Data is available at the out-

-T

OE.

When the CE# pin is

Data Sheet

Related parts for SST27SF020-70-3C-NH

SST27SF020-70-3C-NH Summary of contents

Page 1

... Fast Byte-Program Operation – Byte-Program Time: 20 µs (typical) – Chip Program Time: 1.4 seconds (typical) for SST27SF512 2.8 seconds (typical) for SST27SF010 5.6 seconds (typical) for SST27SF020 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • TTL I/O Compatibility • ...

Page 2

... Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 Product Identification Mode The Product Identification mode identifies the devices as the SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the on OE# hardware method. To activate this mode for SST27SF010/ V ...

Page 3

... UNCTIONAL LOCK IAGRAM OF THE Address Buffer CE# OE PGM for SST27SF020 for SST27SF010 ©2005 Silicon Storage Technology, Inc. SST27SF512 X-Decoder SST27SF010/020 X-Decoder Control Logic 3 Data Sheet SuperFlash Memory Y-Decoder I/O Buffers 1152 B2.1 ...

Page 4

Page 5

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 SST27SF512 A15 1 28 A12 28-pin PDIP Top View DQ0 DQ1 12 17 DQ2 FIGURE ...

Page 6

... IH Program/Erase Inhibit Product Identification can but no other value. IL IH, 2. Device ID = A5H for SST27SF010 and A6H for SST27SF020 Most significant address for SST27SF010 and Note 11.4-12V 11.4-12V PPH H ©2005 Silicon Storage Technology, Inc. ...

Page 7

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...

Page 8

... N Endurance END 1 T Data Retention DR 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 C PERATING HARACTERISTICS FOR (T =25°C±5°C) PPH A Limits Min ...

Page 9

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 AC CHARACTERISTICS TABLE 11 EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time CE# Low to Active Output ...

Page 10

... Recovery Time for Erase Rise Time to 12V during Erase ART Setup Time during Erase A9S Hold Time during Erase A9H 9 ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 T P SST27SF010/020 IMING ARAMETERS FOR 10 Min Max Units 1 µs 1 µs 1 µs 1 µs 50 ...

Page 11

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 ADDRESS CE# OE# HIGH-Z DQ 7-0 FIGURE EAD YCLE IMING ADDRESS (EXCEPT CE# DQ 7-0 V PPH OE#/ PRT V PPH ART FIGURE HIP RASE IMING ©2005 Silicon Storage Technology, Inc. ...

Page 12

... RASE IMING ADDRESS CE# DQ 7-0 HIGH-Z V PPH V DD OE#/ FIGURE YTE ROGRAM IMING ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 SST27SF010/020 IAGRAM FOR ADDRESS VALID DATA VALID T VPS T PRT D SST27SF512 IAGRAM FOR 12 T CEH T VPH ...

Page 13

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 ADDRESS CE# OE 7-0 HIGH-Z V PPH PGM# FIGURE YTE ROGRAM IMING ©2005 Silicon Storage Technology, Inc. ADDRESS VALID DATA VALID T VPS T PRT CES D SST27SF010/020 ...

Page 14

... FIGURE NPUT UTPUT TO DUT FIGURE 10 EST OAD XAMPLE ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 V HT REFERENCE POINTS V LT (0.4 V) for a logic “0”. Measurement reference points for ILT (0.8 V). Input rise and fall times (10 EFERENCE AVEFORMS ...

Page 15

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Start OE#/ PPH Erase 100ms pulse (CE OE#/ Wait for OE#/V PP and A 9 Recovery Time Read Device (CE Compare All bytes to FFH Yes ...

Page 16

... Data Sheet Increment Address No * See Figure 11 FIGURE 13 YTE ROGRAM LGORITHM FOR ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 Start Erase* OE#/ PPH Address = First Location Program 20µs pulse (CE OE#/ Last Address? Yes Wait for OE#/V PP RecoveryTime ...

Page 17

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Address = First Location CE OE Program 20µs pulse Increment Address No * See Figure 12 FIGURE 14 YTE ROGRAM LGORITHM FOR ©2005 Silicon Storage Technology, Inc. Start Erase PPH (PGM ...

Page 18

... SST27SF010-70-3C-WHE Valid combinations for SST27SF020 SST27SF020-70-3C-NH SST27SF020-70-3C-WH SST27SF020-70-3C-NHE SST27SF020-70-3C-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2005 Silicon Storage Technology, Inc. ...

Page 19

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...

Page 20

... All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. 32 LEAD HIN MALL UTLINE SST ACKAGE ODE ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 8.10 7.90 1.20 max. (TSOP ACKAGE 1.05 0.95 0.50 BSC 0.27 0.17 0.15 ...

Page 21

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Pin #1 Identifier .075 .065 Base Plane Seating Plane .050 .015 .080 .065 .070 .045 Note: 1. Complies with JEDEC publication 95 MO-015 AH dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...

Page 22

... Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32 PIN LASTIC UAL N LINE INS SST ACKAGE ODE ©2005 Silicon Storage Technology, Inc. SST27SF512 / SST27SF010 / SST27SF020 1.655 1.645 .200 .170 .150 .120 .100 BSC .022 .016 (PDIP) 22 .625 .600 .550 .530 7˚ 4 PLCS. 0˚ ...

Page 23

... Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 TABLE 14 EVISION ISTORY Number 02 • 2002 Data Book 03 • Document Control Release (SST Internal): No technical changes 04 • Corrected I Supervoltage Current for • Corrected the Test Conditions for I 06 • ...

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