5V995PFGI IDT, 5V995PFGI Datasheet - Page 3

• Manufacturer Part Number: 5V995PFGI
• Description: Clock Drivers & Distribution 3.3V Turbo Clock II
• Manufacturer: IDT
• Type: PLL Clock Driversr

Specifications of 5V995PFGI

• Rohs: yes
• Multiply / Divide Factor: 1
• Output Type: LVTTL
• Max Output Freq: 200 MHz
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Maximum Power Dissipation: 1.9 W
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 250 mA
• Part # Aliases: IDT5V995PFGI

ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
PIN DESCRIPTION
NOTE:
1. When TEST = MID and xsOE = HIGH, PLL remains active with xnF[
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
Symbol
V
V
T
STG
DDQ
I
in effect unless xnF[
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
Pin Name
TEST
xsOE
xDS
xLOCK
xnQ
xnF
GND
, V
V
REF
xFB
xPE
xFS
xPD
V
DDQ
DD
[1:0]
[1:0]
[1:0]
DD
(1)
(1)
Supply Voltage to Ground
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
Storage Temperature Range
PWR
PWR
PWR
Type
OUT
OUT
1:0
I N
I N
I N
I N
I N
I N
I N
I N
I N
] = LL.
Description
Description
Reference Clock Input
Individual Feedback Inputs for A and B banks
When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See
Control Summary Table) remain in effect. Set LOW for normal operation.
Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q
(for xPE = H) - x2Q
is HIGH, the nF[
(has internal pull-down).
Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/
positive edge of the reference clock (has internal pull-up).
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A
and B banks.
Eight banks of two outputs with programmable skew
3-level inputs for feedback divider selection for A and B banks
Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up).
PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronized to the inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
Power supply for output buffers
Power supply for phase locked loop, lock output, and other internal circuitry
Ground
T
T
A
A
= 85°C
= 55°C
1:0
] pins act as output disable controls for individual banks when xnF[
0
and x2Q
–0.5 to V
–0.5 to +5.5
–0.5 to +4.6
–65 to +150
Max
1.1
1.9
1
DD
may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE
(1)
+0.5
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain
Unit
°C
W
V
V
V
3
CAPACITANCE
NOTE:
1. Capacitance applies to all inputs except TEST, xFS, xnF
Parameter
C
IN
Description
Input Capacitance
(T
A
1:0
INDUSTRIAL TEMPERATURE RANGE
= +25°C, f = 1MHz, V
] = LL. Set xsOE LOW for normal operation
REF
Others
0
and x2Q
Typ.
8
5
[1:0]
IN
= 0V)
, and xDS
1
) in a LOW state
Max.
10
7
[1:0]
.
Unit
pF