8536AG-02LF IDT, 8536AG-02LF Datasheet

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8536AG-02LF

Manufacturer Part Number
8536AG-02LF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8536AG-02LF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS8536AG-02LF
XTAL_OUT0
XTAL_OUT1
Block Diagram
ICS8536AG-02 REVISION A JULY 21, 2010
General Description
The ICS8536-02 is a low skew, high performance 1-to-6, Dual
Crystal or LVCMOS Input-to-3.3V, 2.5V LVPECL Fanout Buffer. The
ICS8536-02 has selectable crystal or single ended clock input. The
single ended clock input accepts LVCMOS or LVTTL input levels and
translates them to LVPECL levels. The output enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8536-02 ideal for those applications demanding well defined
performance and repeatability.
CLK_SEL0
CLK_SEL1
XTAL_IN0
XTAL_IN1
CLK_EN
CLK0
Pullup
Pulldown
Pulldown
Pulldown
OSC
OSC
00
01
1X
Low Skew, 1-to-6, Dual Crystal/LVCMOS-to-
3.3V, 2.5V LVPECL Fanout Buffer
D
LE
Q
6 LVPECL Outputs
Q0
nQ0
Q5
nQ5
1
Features
Six 3.3V, 2.5V differential LVPECL output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Maximum output frequency: 266MHz
Crystal frequency range: 14MHz – 40MHz
Output skew: 55ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 1.85ns (maximum), 3.3V
Additive phase jitter, RMS: 0.149ps (typical)
Full 3.3V or 2.5V supply modes
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
4.4mm x 7.8mm x 0.925mm package body
Pin Assignment
XTAL_OUT0
CLK_SEL0
XTAL_IN0
CLK_EN
nQ2
nQ1
nQ0
V
V
24-Lead TSSOP
Q2
Q1
Q0
CC
EE
ICS8536-02
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
12
©2010 Integrated Device Technology, Inc.
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
V
Q4
nQ4
V
Q5
CLK_SEL1
XTAL_IN1
XTAL_OUT1
CC
CC
ICS8536-02
DATA SHEET

Related parts for 8536AG-02LF

8536AG-02LF Summary of contents

Page 1

... CLK_SEL1 XTAL_IN0 OSC 00 XTAL_OUT0 XTAL_IN1 OSC 01 XTAL_OUT1 Pulldown CLK0 1X ICS8536AG-02 REVISION A JULY 21, 2010 Features • Six 3.3V, 2.5V differential LVPECL output pairs • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Maximum output frequency: 266MHz • Crystal frequency range: 14MHz – 40MHz • ...

Page 2

... Input Capacitance IN R Input Pullup Resistor PULLUP R Input Pulldown Resistor PULLDOWN ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Type Description Differential output pair. LVPECL interface levels. Power supply pins. Differential output pair. LVPECL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. ...

Page 3

... After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the selected clock input. CLK0, XTAL0, XTAL1 CLK_EN nQ[0:5] Q[0:5] Figure 1. CLK_EN Timing Diagram ICS8536AG-02 REVISION A JULY 21, 2010 Inputs CLK_SEL0 Selected Source 0 XTAL0 1 XTAL1 ...

Page 4

... V Input Low Voltage IL CLK0, CLK_SEL[0:1] Input I IH High Current CLK_EN CLK0, CLK_SEL[0:1] Input I IL Low Current CLK_EN ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Rating 4. -0. 0.5V CC 50mA 100mA 87.8°C/W (0 mps) -65°C to 150°C = 3.3V ± 0°C to 70°C ...

Page 5

... NOTE 1: Outputs terminated with 50 Table 5. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER = 3.3V ± Test Conditions to V – 2V. ...

Page 6

... NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6: Measured on either XTAL0 or XTAL1 when single-ended CLK0 switching at 150MHz or 250MHz. ICS8536AG-02 REVISION A JULY 21, 2010 = 3.3V ± 0° ...

Page 7

... This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...

Page 8

... LVPECL Output Load AC Test Circuit Par t 1 nQx Qx Par t 2 nQy Qy tsk(pp) Part-to-Part Skew CLK0 nQ[0:5] Q[0: Propagation Delay ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER 2V SCOPE LVPECL nQx V EE -0.5V ± 0.125V 2.5V LVPECL Output Load AC Test Circuit nQx Qx nQy Qy Output Skew ...

Page 9

... CLK0 input to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER A0 80% V ...

Page 10

... Ohm LVPECL R2 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER 18pF Parallel Crystal Figure 2. Crystal Input Interface matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance ...

Page 11

... Figure 4A. 3.3V LVPECL Output Termination ICS8536AG-02 REVISION A JULY 21, 2010 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may ...

Page 12

... LVPECL Driver Figure 5A. 2.5V LVPECL Driver Termination Example V = 2.5V CCO 50Ω 50Ω 2.5V LVPECL Driver Figure 5C. 2.5V LVPECL Driver Termination Example ICS8536AG-02 REVISION A JULY 21, 2010 ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. – very close to CC 2.5V 2.5V R3 250 + – ...

Page 13

... This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). θ Table 7. Thermal Resitance for 24 Lead TSSOP, Forced Convection JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8536AG-02 REVISION A JULY 21, 2010 = 3. 3.465V, which gives worst case results 3.465V * 89mA = 308.385mW EE_MAX * Pd_total + θ ...

Page 14

... Pd_L is the power dissipation when the output drives low. Pd_H = [(V – (V – 2V))/R OH_MAX CC_MAX [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V (V – 2V))/R OL_MAX CC_MAX [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS8536AG-02 REVISION A JULY 21, 2010 V OUT RL 50Ω – 0.9V CC_MAX = V – 1.7V ...

Page 15

... JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS8536-02 is: 467 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP ICS8536AG-02 REVISION A JULY 21, 2010 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER θ vs. Air Flow 87.8°C/W 83.5° ...

Page 16

... ICS8536AG-02 8536AG-02LF ICS8536AG-02L 8536AG-02LFT ICS8536AG-02L NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 17

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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