85105AGILF IDT, 85105AGILF Datasheet

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85105AGILF

Manufacturer Part Number
85105AGILF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 85105AGILF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS85105AGILF
B
CLK_SEL
ICS85105AGI REVISION A MAY 27, 2011
G
The ICS85105I is a low skew, high performance 1-to-5 Differ-
ential-to-0.7V HCSL Fanout Buffer. The ICS85105I has two
selectable clock inputs. The CLK0, nCLK0 pair can accept most
standard differential input levels. The single-ended CLK1 can
accept LVCMOS or LVTTL input levels. The clock enable is in-
ternally synchronized to eliminate runt clock pulses on the out-
puts during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85105I ideal for those applications demanding well
defined performance and repeatability.
CLK_EN
nCLK0
LOCK
CLK0
ENERAL
CLK1
IREF
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
D
IAGRAM
D
ESCRIPTION
0
1
Low Skew, 1-to-5, Differential/LVCMOS-
to-0.7V HCSL Fanout Buffer
LE
D
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
P
F
Five 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximuml)
Additive phase jitter, RMS: 0.24ps (typical)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IN
EATURES
A
SSIGNMENT
6.5mm x 4.4mm x 0.925mm Package Body
CLK_SEL
CLK_EN
nCLK0
CLK0
CLK1
GND
IREF
nQ4
V
Q4
20-Lead TSSOP
DD
ICS85105I
G Package
Top View
1
2
3
4
5
6
7
8
9
10
2011 Integrated Device Technology, Inc.
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
V
Q3
nQ3
DD
DD
ICS85105I
DATA SHEET

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85105AGILF Summary of contents

Page 1

Low Skew, 1-to-5, Differential/LVCMOS- to-0.7V HCSL Fanout Buffer G D ENERAL ESCRIPTION The ICS85105I is a low skew, high performance 1-to-5 Differ- ential-to-0.7V HCSL Fanout Buffer. The ICS85105I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most ...

Page 2

ICS85105I Data Sheet ABLE IN ESCRIPTIONS ...

Page 3

ICS85105I Data Sheet ABLE ONTROL NPUT UNCTION ...

Page 4

ICS85105I Data Sheet BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance Lead TSSOP Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...

Page 5

ICS85105I Data Sheet ABLE HARACTERISTICS ...

Page 6

ICS85105I Data Sheet The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and ...

Page 7

ICS85105I Data Sheet P ARAMETER 3.3V±10 HCSL 50 IREF GND 475 0V This load condition is used for sk(o HCSL UTPUT OAD EST IRCUIT V DD nCLK0 ...

Page 8

ICS85105I Data Sheet P ARAMETER Clock Period (Differential) Positive Duty Cycle (Differential) 0. IFFERENTIAL EASUREMENT OINTS FOR T STABLE V RB +150mV V = +100mV RB 0. -100mV RB -150mV Q - ...

Page 9

ICS85105I Data Sheet R U ECOMMENDATIONS FOR NUSED I : NPUTS CLK I NPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection resistor can ...

Page 10

... LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination 3 ...

Page 11

ICS85105I Data Sheet R T ECOMMENDED ERMINATION Figure 4A is the recommended source termination for applications where the driver and receiver will be on separate PCBs. This termination is the standard for PCI Express and 0.5" Max ...

Page 12

ICS85105I Data Sheet This section provides information on power dissipation and junction temperature for the ICS85105I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85105I is the sum of the core power ...

Page 13

ICS85105I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 5. R REF = 475 HCSL ...

Page 14

ICS85105I Data Sheet ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS85105I is: 614 ...

Page 15

... Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ...

Page 16

ICS85105I Data Sheet ICS85105AGI REVISION A MAY 27, 2011 LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V ...

Page 17

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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