FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 4

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

Overview
The FM33256B device combines a serial nonvolatile
RAM with a real-time clock (RTC) and a processor
companion. The companion is a highly integrated
peripheral including a processor supervisor, analog
comparator, a nonvolatile counter, and a serial
number.
complementary but distinct functions under a
common interface in a single package. The product is
organized as two logical devices. The first is a
memory and the second is the companion which
includes all the remaining functions. From the system
perspective they appear to be two separate devices
with unique op-codes on the serial bus.
The memory is organized as a standalone nonvolatile
SPI memory using standard op-codes. The real-time
clock and supervisor functions are accessed under
their own op-codes. The clock and supervisor
functions are controlled by 30 special function
registers. The RTC/alarm and some control registers
are maintained by the power source on the VBAK
pin, allowing them to operate from battery or backup
capacitor power when V
threshold. Each functional block is described below.
Memory Operation
The FM33256B is available with 256Kb of memory.
The device uses two-byte addressing for the memory
portion of the chip. This makes the device software
compatible with its standalone memory counterparts,
such as the FM25W256.
Memory is organized in bytes. The 256Kb memory is
32,768 x 8. The memory is based on F-RAM
technology. Therefore it can be treated as RAM and
is read or written at the speed of the SPI bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The SPI protocol is described
on page 18.
The memory array can be write-protected by
software. Two bits (BP0, BP1) in the Status Register
control the protection setting. Based on the setting,
the protected addresses cannot be written. The Status
Register & Write Protection is described in more
detail on page 20.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
The
FM33256B
DD
drops below a set
integrates
these
Processor Companion
In addition to nonvolatile RAM, the FM33256B
incorporates a real-time clock with alarm and highly
integrated processor companion. The companion
includes a low-V
timer, a 16-bit nonvolatile event counter, a
comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic
functions: Detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. The FM33256B has a reset pin (/RST) to
drive a processor reset input during power faults,
power-up, and software lockups. It is an open drain
output with a weak internal pull-up to V
allows other reset sources to be wire-OR’d to the
/RST pin. When V
point, /RST output is pulled weakly to V
drops below the reset trip point voltage level (V
the /RST pin will be driven low. It will remain low
until V
the V
/RST continues to drive low for at least 50 ms (t
to ensure a robust system reset at a reliable V
After t
the weak high state. While /RST is asserted, serial
bus activity is locked out even if a transaction
occurred as V
operation started while V
completed internally.
Table 1 below shows how bits VTP(1:0) control the
trip point of the low-V
register 18h, bits 0 and 1. The reset pin will drive
low when V
the SPI interface and F-RAM array will be locked
out. Figure 2 illustrates the reset operation in
response to a low V
RST
RPU
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VTP Setting
falls too low for circuit operation which is
level. When V
has been met, the /RST pin will return to
DD
2.75V
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
2.6V
2.9V
3.0V
is below the selected V
DD
DD
dropped below V
Ramtron International Corporation
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reset, a programmable watchdog
.
Table 1.
is above the programmed trip
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VTP1
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(800) 545-FRAM, [phone]
reset. They are located in
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0
0
1
1
rises again above V
is above V
VTP0
0
1
0
1
www.ramtron.com
TP
TP
. A memory
voltage, and
TP
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Page 4 of 28
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. If V
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will be
. This
level.
RPU
TP
TP
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,