DS1020S-50+W Maxim Integrated, DS1020S-50+W Datasheet - Page 7

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DS1020S-50+W

Manufacturer Part Number
DS1020S-50+W
Description
Delay Lines / Timing Elements
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS1020S-50+W

Rohs
yes
CAPACITANCE
TIMING DIAGRAM: SILICON DELAY LINE Figure 5
(cont’d)
PARAMETER
Parallel Input Change
to Delay Invalid
Enable to Delay Valid
Enable to Delay Invalid
V
Functional
Input Pulse Width
Input to Output Delay
Input Period
PARAMETER
Input Capacitance
CC
Valid to Device
SYMBOL
SYMBOL
t
PLH
Period
t
t
t
C
t
t
PDX
EDV
EDX
PU
WI
, t
IN
PHL
100% of Output
2 (t
Delay
MIN
MIN
7 of 9
0
0
WI
)
Table 2
TYP
TYP
MAX
MAX
100
50
10
UNITS
UNITS
ms
pF
µs
ns
ns
ns
ns
ns
(T
A
= 25°C)
NOTES
NOTES
2

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