MAX11607EWC+T Maxim Integrated, MAX11607EWC+T Datasheet - Page 14
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MAX11607EWC+T
Manufacturer Part Number
MAX11607EWC+T
Description
Analog to Digital Converters - ADC 10-Bit 4Ch 94.4sps 3.6V Precision ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX11607EWCT.pdf
(22 pages)
Specifications of MAX11607EWC+T
Rohs
yes
Number Of Channels
4/2
Architecture
SAR
Conversion Rate
94.4 Ksps
Resolution
10 bit
Input Type
Single-Ended/Differential
Snr
60 dB
Interface Type
I2C
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
WLP-12
Maximum Power Dissipation
1.288 W
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
2.048 V
Low-Power, 4-/8-/12-Channel, I
10-Bit ADCs in Ultra-Small Packages
Table 2. Configuration Byte Format
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
1
2
14
For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.
When SEL1 = 1, a single-ended read of AIN3/REF (MAX11606/MAX11607) or AIN11/REF (MAX11610/MAX11611) is ignored; scan
stops at AIN2 or AIN10. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF.
CS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(MSB)
______________________________________________________________________________________
BIT 7
1
REG
BIT
7
6
5
4
3
2
1
0
CS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
CS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SGL/DIF
SCAN1
SCAN1
SCAN0
NAME
BIT 6
REG
CS3
CS2
CS1
CS0
CS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
+
Register bit. 1= setup byte (see Table 1), 0 = configuration byte.
S can sel ect b i ts. Tw o b i ts sel ect the scanni ng confi g ur ati on ( Tab l e 5) . D efaul ts to 00 at p ow er - up .
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3 and 4). Defaults to 0000 at power-up. For MAX11606/MAX11607, CS3 and CS2 are
internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.
1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-
Ended/Differential Input section.
SCAN0
BIT 5
AIN1
+
AIN2
+
BIT 4
AIN3
CS3
+
2
AIN4
+
AIN5
BIT 3
CS2
+
DESCRIPTION
RESERVED
RESERVED
RESERVED
RESERVED
AIN6
+
2
C,
AIN7
BIT 2
+
CS1
AIN8
+
AIN9 AIN10 AIN11
+
BIT 1
CS0
+
SGL/DIF
+
(LSB)
BIT 0
2
GND
-
-
-
-
-
-
-
-
-
-
-
-