MAX11662AUB+T Maxim Integrated, MAX11662AUB+T Datasheet - Page 12

• Manufacturer Part Number: MAX11662AUB+T
• Description: Analog to Digital Converters - ADC 12/10/8Bit 500ksps Low Power Serial
• Manufacturer: Maxim Integrated

Specifications of MAX11662AUB+T

• Rohs: yes
• Number Of Channels: 2
• Architecture: SAR
• Conversion Rate: 500 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 2.2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 707.3 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.2 V to 3.6 V

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11662) (continued)
(V
unless otherwise noted. Typical values are at T
12
DIGITAL INPUTS (SCLK, CS)
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Hysteresis
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage
Output Low Voltage
High-Impedance Leakage
Current
High-Impedance Output
Capacitance
POWER SUPPLY
Positive Supply Voltage
Digital I/O Supply Voltage
Positive Supply Current
(Full-Power Mode)
Positive Supply Current
(Full-Power Mode), No Clock
Power-Down Current
Line Rejection
TIMING CHARACTERISTICS (Note 2)
Quiet Time
CS Pulse Width
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
Data Access Time After SCLK
Falling Edge (Figure 2)
SCLK Pulse Width Low
SCLK Pulse Width High
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High
Impedance
Power-Up Time
DD
_____________________________________________________________________________________
= 2.2V to 3.6V, V
PARAMETER
REF
= V
DD
, V
OVDD
SYMBOL
V
V
I
C
OVDD
I
I
V
V
V
OVDD
V
HYST
C
VDD
VDD
I
I
V
OUT
I
t
OL
PD
OH
DD
t
t
t
t
t
t
t
t
OL
IL
Q
IH
IL
IN
1
2
3
4
5
6
7
8
= V
DD
A
, f
= +25NC.) (Note 1)
Inputs at GND or V
I
I
V
V
Leakage only
V
(Note 3)
(Note 3)
(Note 3)
(Note 3)
V
V
Percentage of clock period
Percentage of clock period
Figure 3
Figure 4 (Note 3)
Conversion cycle (Note 3)
SOURCE
SINK
AIN_
AIN_
DD
OVDD
OVDD
SCLK
= 2.2V to 3.6V, V
= 200µA (Note 3)
= V
= V
= 8MHz, 50% duty cycle, 500ksps, C
= 2.2V to 3.6V (Note 3)
= 1.5V to 2.2V (Note 3)
= 200µA (Note 3)
GND
GND
CONDITIONS
DD
REF
= 2.2V
DOUT
V
V
0.75 x
0.85 x
OVDD
OVDD
MIN
2.2
1.5
2.5
10
40
40
4
5
1
5
= 10pF, T
V
0.15 x
0.001
TYP
OVDD
0.17
1.5
1.3
2
4
A
= -40NC to +125NC,
V
V
0.25 x
0.15 x
MAX
Q1.0
1.67
16.5
OVDD
OVDD
V
3.6
0.1
Q1
10
15
60
60
14
DD
1
UNITS
LSB/V
Cycle
mA
mA
FA
pF
FA
pF
FA
ns
ns
ns
ns
ns
ns
ns
%
%
V
V
V
V
V
V
V