74LVCZ161284ATTR STMicroelectronics, 74LVCZ161284ATTR Datasheet

74LVCZ161284ATTR

Manufacturer Part Number

74LVCZ161284ATTR

Description

IC TXRX LV HS IEEE 1284 48-TSSOP

Manufacturer

STMicroelectronics

Series

74LVCZr

Datasheet

1.74LVCZ161284ATTR.pdf (12 pages)

Specifications of 74LVCZ161284ATTR

Logic Type

IEEE STD 1284 Translation Transceiver

Supply Voltage

3 V ~ 3.6 V

Number Of Bits

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

497-1079-2

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Part Number

Manufacturer

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Price

Company:

BOSTOCK HK LIMITED

Part Number:

74LVCZ161284ATTR

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DESCRIPTION

The 74LVCZ161284A contains eight high speed

non inverting bidirectional buffers and eleven

control/status non-inverting buffers with open

drain outputs fabricated in silicon gate C

technology. It’s intended to provide a standard

signaling method for a bi-direction parallel

peripheral in an Extended Capabilities Port Mode

(ECP). The HD (Active HIGH) input pin enables

the Cable port to switch from Open Drain to a high

drive totem pole output, capable of sourcing 14mA

on all thirteen buffer and 84mA on PERI LOGIC

OUTPUT buffer. The DIR input determines the

direction of data flow on the bidirectional buffers.

DIR (Active HIGH) enables data flow from A port

to B port. DIR (Active LOW) enables data flow

from B port to A port. The Y output (Y9-Y13) stay

in the high state after power-on until an associated

input A9-A13) goes high. When an associated

input goes high, all Y outputs are active, and non

July 2005

HIGH SPEED: t

LOW POWER DISSIPATION:

TTL COMPATIBLE INPUTS

OPERATING VOLTAGE RANGE:

A PORT HAVE STANDARD 4mA TOTEM

POLE OUTPUT

B PORT HIGH DRIVE SOURCE/SINK

CAPABILITY OF 14mA

AUTO POWER-UP FEATURE TO PREVENT

PRINTER ERRORS

SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)

AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR

BIDIRECTIONAL PARALLEL

COMMUNICATIONS BETWEEN PERSONAL

COMPUTER ANT PRINTING PERIPHERALS

TRANSLATION CAPABILITY ALLOW

OUTPUTS ON CABLE SIDE TO INTERFACE

WITH 5V SIGNAL

PULL-UP RESISTOR INTEGRATED ON ALL

OPEN-DRAIN OUTPUT ELIMINATE THE

NEED FOR DISCRETE RESISTOR

REPLACE THE FUNCTION OF TWO

74LVC1284 DEVICES

=20µA (MAX) at V

=2V (MIN) V

(OPR) = 3.0V to 3.6V

LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER

=0.8(MAX)

= 9ns (MAX.) at V

=3.6V T

=85°C

= 3V

MOS

WITH ERROR-FREE POWER-UP

ORDER CODES

PIN CONNECTION

PACKAGE

TSSOP

74LVCZ161284A

TUBE

TSSOP

74LVCZ161284ATTR

T & R

1/12

Related parts for 74LVCZ161284ATTR

74LVCZ161284ATTR Summary of contents

Page 1

... A9-A13) goes high. When an associated input goes high, all Y outputs are active, and non July 2005 WITH ERROR-FREE POWER- =85°C A ORDER CODES PACKAGE TSSOP PIN CONNECTION 2 MOS 74LVCZ161284A TSSOP TUBE T & R 74LVCZ161284ATTR 1/12 ...

Page 2

Y outputs. This special feature prevents printer system errors deasserting the BUSY signal in the cable at LOGIC DIAGRAM NOTE A: The PMOS transistors prevent backdriving current from the signal ...

Page 3

PIN DESCRIPTION PIN N° 11, 12, 13, 14, 16 20, 21, 22 29, 28, 27 41, 40, 38, 37, 36, 35, 33, 32 47, 46, ...

Page 4

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage CC Cable Supply Voltage (must be ≥ CCcable V DC Input Voltage A1-A13 Input Voltage B1-B8, C14-C17 Input Voltage B1-B8, C14-C17, HL ...

Page 5

DC SPECIFICATIONS Symbol Parameter V High Level An, Bn Input Voltage Low Level An, Bn Input Voltage High Level An Output Voltage Bn, Yn Bn, Yn ...

Page 6

AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Propagation A1-A8 to B1-B8, PLH Delay Time A9-A13 to Y9-Y13 t PHL B1-B8 to A1-A8, C14-C17 to A14-A17 Enable Delay DIR to A PZH ...

Page 7

TEST CIRCUIT t (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLH PHL t (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLH PLH (see waveform (B1-B8 to A1-A8, C14-C17 to A14-A17, HLH PHL PLH (A1-A8 to ...

Page 8

WAVEFORM 2: PROPAGATION DELAY INPUT An TO OUTPUT (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY INPUT Bn TO OUTPUT (f=1MHz; 50% duty cycle 50 74LVCZ161284A 8/12 ...

Page 9

WAVEFORM 4: DATA TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) WAVEFORM 5: DIR TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74LVCZ161284A 9/12 ...

Page 10

DIM. MIN 0. 0.17 c 0. 0° PIN 1 IDENTIFICATION 1 10/12 TSSOP48 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 0.9 0.27 ...

Page 11

Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 13.3 0.516 ...

Page 12

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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