AS1542-BTSU ams, AS1542-BTSU Datasheet - Page 12

• Manufacturer Part Number: AS1542-BTSU
• Description: Analog to Digital Converters - ADC
• Manufacturer: ams

Specifications of AS1542-BTSU

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 1 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 18.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

AS1542
Data Sheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1542 is a fast, 16-channel, 12-bit, single-supply, A/D converter, which can be operated from a 2.7 to 5.25V sup-
ply. The AS1542 is capable of throughput rates of up to 1Msps when provided with a 20MHz clock. The AS1542 fea-
tures on-chip track/hold, A/D converter, sequencer and a serial interface in a TSSOP-28 package.
The AS1542 has 16 single-ended or 8 fully-differential input channels with a channel sequencer, allowing the selection
of the sequence of channels the ADC can cycle through on (each consecutive CSN falling edge). The serial clock input
accesses data from the AS1542, controls the transfer of data written to the ADC, and provides the clock source for the
successive-approximation A/D converter.
The analog input range for the AS1542 is [0 to V
[-V
RANGE (page 14)
to 5.25V supply.
The AS1542 provides flexible power management options (see bits
best power performance for a given throughput rate.
Converter Operation
The AS1542 is a 12-bit successive approximation analog-to-digital converter based around a capacitive DAC. The
AS1542 can convert analog input signals in the range [0V to V
[-V
Figure 21
SAR, and a capacitive DAC, which are used to redistribute fixed amounts of charge with the capacitive DAC to bring
the comparator back into a balanced condition.
and input switch are closed. The comparator is held in a balanced condition and the sampling capacitors C
acquires the signal on the selected V
Figure 21. Data Acquisition
When a conversion is started
become unbalanced. The control logic and the capacitive DAC are used to redistribute fixed amounts of charge from
the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is re-balanced,
the conversion is complete. Control logic generates the ADC output code.
See
www.austriamicrosystems.com
REFIN
REFIN
page 16
C
SWITCH
/2 to +V
/2 to +V
and
Analog Input
CH15
AGND
includes all parasitics
for the ADC transfer functions.
Multiplexer
CH0
CH1
CH2
CH3
CH4
CH5
Figure 22
REFIN
REFIN
and
/2] or [-V
/2] or [-V
SE/FDN (page
show simplified diagrams of the ADC operation. The ADC circuitry is made up of control logic,
(see Figure
REFIN
REFIN
AIN+
AIN-
to +V
to +V
INx
14). For the [0V to 2 x V
C
C
SWITCH
SWITCH
channel.
11pF
11pF
REFIN
REFIN
Input
Switch
Input
Switch
22), sample switch and input switch opens causing the comparator to
] for 8 fully differential input channels depending on the setting of bit
] .
Figure 21
REFIN
REFIN
S&H and capacitive DAC
Revision 1.00
C
C
] or [0V to 2 x V
13pF
13pF
–
–
HOLD
HOLD
+
+
shows the ADC during its acquisition phase. Sample switch
REFIN
REFIN
Sample
Switch
R
IN
PM1, PM0 (page 14)
] or [0V to 2 x V
] mode, the device must be operated from a 4.75
REFIN
] for 16 single ended input channels or
AGND
REFIN
+
–
] or
of the control register) for the
Comparator
Control
Logic
HOLD
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