IS46TR16128A-15HBLA1-TR ISSI, IS46TR16128A-15HBLA1-TR Datasheet - Page 68

• Manufacturer Part Number: IS46TR16128A-15HBLA1-TR
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA1-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
9.3 Jitter Notes
Specific Note a
Unit “tCK(avg)” represents the actual tCK(avg) of the input clock under operation. Unit “nCK” represents one clock cycle of
the input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is
registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) +
tERR(4per), min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc)
transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal
(CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as
these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or
not.
Specific Note d
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective
data strobe signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is in
clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP
=RU{tRP/tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-
6, of which tRP = 15ns, the device will support tnRP = RU{tRP/tCK(avg)} = 6, as long as the input clock jitter specifications
are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6-Tm) is less than 15ns due to
input clock jitter.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Write leveling setup time from rising CK, CK#
DQS/DQS# delay after write leveling mode is
ODT high time with Write command and BL8
RTT_Nom and RTT_WR turn-off time from
DQS# crossing to rising CK, CK# crossing
Asynchronous RTT turn-on delay (Power-
Asynchronous RTT turn-off delay (Power-
Write leveling hold time from rising DQS,
First DQS/DQS# rising edge after write
crossing to rising DQS, DQS# crossing
leveling mode is programmed
RTT dynamic change skew
Write leveling output delay
Write leveling output error
Down with DLL frozen)
Down with DLL frozen)
Write Leveling Timings
ODTLoff reference
programmed
RTT turn-on
Parameter
tWLDQSEN
tWLMRD
tAONPD
tAOFPD
Symbol
ODTH8
tWLOE
tAON
tWLS
tWLH
tWLO
tAOF
tADC
DDR3/DDR3L-1866
Min.
-195
140
140
0.3
0.3
40
25
2
2
0
0
Max.
ODTH8max.: -
ODTH8min.: 6
195
8.5
8.5
0.7
0.7
7.5
2
-
-
-
-
DDR3/DDR3L-1866
Min.
Max.
tCK(avg)
tCK(avg)
Units
nCK
nCK
nCK
ns
ns
ps
ps
ps
ns
ns
68
Notes
7,f
8,f
3
f