SSTV16859G Fairchild Semiconductor, SSTV16859G Datasheet
SSTV16859G
Specifications of SSTV16859G
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SSTV16859G Summary of contents
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... The device has been fabricated on an advanced sub- micron CMOS process and is designed to operate at power supplies of less than 3.6V’s. Ordering Code: Order Number Package Number SSTV16859G BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) SSTV16859MTD MTD64 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6 ...
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Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Name Description Q -Q SSTL-2 Compatible Register Outputs 1A 13A 13B D -D SSTL-2 Compatible Register Inputs 1 13 RESET ...
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Functional Description The SSTV16859 is a 13-bit dual register with SSTL-2 com- patible inputs and outputs. Input data is transferred to out- put data on the rising edge of the differential clock pair. When the RESET signal is asserted LOW ...
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Absolute Maximum Ratings Supply Voltage (V ) DDQ Supply Voltage ( Reference Voltage (V ) REF Input Voltage ( Output Voltage ( Outputs Active (Note 4) 0. Input ...
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DC Electrical Characteristics Symbol Parameter R Output HIGH On Resistance OH R Output LOW On Resistance Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Pulse Duration, CK, ...
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AC Loading and Waveforms Note: C includes probe and jog capacitance L FIGURE 1. AC Test Circuit Note: I tested with clock and data inputs held and I 0 mA. O FIGURE 3. Voltage and Current ...
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Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...