ZADCS1222IS14T ZMDI, ZADCS1222IS14T Datasheet - Page 22
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ZADCS1222IS14T
Manufacturer Part Number
ZADCS1222IS14T
Description
Analog to Digital Converters - ADC ADC
Manufacturer
ZMDI
Datasheet
1.ZADCS1222IS14T.pdf
(26 pages)
Specifications of ZADCS1222IS14T
Product Category
Analog to Digital Converters - ADC
Rohs
yes
Number Of Channels
2/1
Architecture
SAR
Conversion Rate
200 KSPs
Resolution
12 bit
Input Type
Single-Ended/Differential
Snr
70 dB
Interface Type
Microwire, QSPI, SPI
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-14
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 25 C
Number Of Converters
1
Voltage Reference
2.5 V
Output Code Format
ZADCS12x2 family devices do all support unipolar and bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x00 for an input voltage difference of 0V to 0xFF for an input
voltage difference of VREF (Full Scale = FS). The first code transition (0x00 0x01) occurs at a voltage
equivalent to ½ LSB, the last (0xFE 0xFF) at VREF-1.5 LSB. See also Figure 16 for details. In bipolar
mode a two’s complement coding is applied. Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in Figure 17.
Figure 16: Unipolar Transfer Function
2.5.
The ZADCS12x2 family offers three different ways to save operating current between conversions. Two
different software controlled power down modes can be activated to automatically shut-down the device after
completion of a conversion. They differ in the amount of circuitry that is powered down.
Software Power Down
Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to
less than 0.5µA if no external clock is provided at SCLK. Fast Power Down mode is only useful with
ZADCS12x2V devices if the internal voltage reference is used. During Fast Power-Down the bandgap and the
VREFADJ output buffer are kept alive while all other internal analog circuitry is shut down. The benefit of Fast
Power Down mode is a shorter turn on time of the reference compared to Full Power-Down Mode. This is
basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20kΩ
resistor and the external buffer capacitor of 47nF is not discharged in Fast Power-Down Mode. The settling
time of the low pass at VREFADJ is about 9ms to reach 12 bit accuracy. The Fast Power Down mode omits
this settling and reduces the turn on time to about 200µs. To wake up the IC out of either software power
down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly
transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device.
In all application cases where an external reference voltage is supplied (basic ZADCS12x2 and ZADCS12x2V
with VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid.
Fast Power-Down and Full Power-Down Mode do not show any difference in this configuration.
Data Sheet
October 12, 2011
00 … 000
11 … 111
11 … 110
11 … 101
00 … 010
00 … 001
ZADCS1282/1242/1222
12-Bit, 200ksps, ADC Family
Output Code
Power Dissipation
(ZS)
0
1
2 3
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
Input Voltage (LSB)
FS-3/2 LSB
ZS = V(IN-)
FS = V
)
1LSB =
FS
REF
V
4096
REF
+V(IN-
Figure 17: Bipolar Transfer Function
10 … 000
01 … 111
01 … 110
00 … 011
00 … 001
00 … 000
11 … 111
11 … 110
11 … 101
10 … 001
Output Code
-FS
+ FS = ½V
- FS = -½V
1LSB =
ZS = V(IN-)
Input Voltage (LSB)
V
4096
REF
REF
REF
+V(IN-)
+V(IN-)
ZS
+FS-3/2 LSB
+FS
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