ZADCS1242IS16T ZMDI, ZADCS1242IS16T Datasheet - Page 20

• Manufacturer Part Number: ZADCS1242IS16T
• Description: Analog to Digital Converters - ADC ADC
• Manufacturer: ZMDI

Specifications of ZADCS1242IS16T

• Product Category: Analog to Digital Converters - ADC
• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: Microwire, QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-16
• Maximum Power Dissipation: 250 mW
• Minimum Operating Temperature: - 25 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Figure 13: 16-Clock External Clock Mode Conversion
Figure 14: 15-Clock External Clock Mode Conversion
Internal Clock Mode
In Internal Clock Mode, the conversion starts at the falling clock edge of the eighth control bit just as in
External Clock Mode. However, there are no further clock pulses required at SCLK to complete the
conversion. The conversion clock is generated by an internal oscillator that runs at approximately 3.2MHz.
While the conversion is running, the SSTRB signal is driven LOW. As soon as the conversion is complete,
SSTRB is switched to HIGH, signalling that the conversion result can be read out on the serial interface. To
shorten cycle times ZADCS12x2 family devices allow interleaving of the read out process with the
transmission of a new control byte. Thus it is possible to read the conversion result and to start a new
conversion with just two consecutive byte transfers, instead of thee bytes that would have to be send without
the interleaving function. While the IC is performing a conversion in Internal Clock Mode, the Chip Select
signal (nCS) may be tied HIGH allowing other devices to communicate on the bus. The output driver at DOUT
is switched into a high impedance state while nCS is HIGH. The conversion time t
specified limits depending on the actual VDD and temperature values.
16-Clocks per Conversion
Interleaving of the data read out process and transmission of a new Control Byte is also supported for
External Clock Mode operation. Figure 13 shows the transmission timing for conversion runs using 16 clock
cycles per run.
15-Clocks per Conversion
ZADCS12x2 family devices do also support a 15 clock cycle conversion mode (see Figure 14). This is the
fastest conversion mode possible. In fact, the specified converter sampling rate of 200ksps will be reached in
this mode, provided the clock frequency is set to 3.2MHz. Usually micro controllers do not support this kind of
15 bit serial communication transfers. However, specifically designed digital state machines implemented in
Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this
operation mode.
Data Sheet
October 12, 2011
DOUT
SSTRB
SCLK
SSTR
DOUT
ZADCS1282/1242/1222
12-Bit, 200ksps, ADC Family
SCLK
nCS
DIN
nCS
DIN
(Start)
S
1
A2 A1 A0
Idle
(Start)
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
S
1
A2 A1 A0
Idle
UNI/
BIP
SGL/
DIF
Acquire
PD1 PD0
UNI/
BIP
SGL/
DIF
8
Acquire
PD1 PD0
(MSB)
B11 B10 B9 B8 B7 B6 B5
8
1
(MSB)
B11 B10 B9 B8 B7 B6 B5
Conversion
1
Conversion
S
1
A2 A1 A0
B4
B3 B2 B1 B0
8
UNI/
BIP
B4
(LSB)
S
SGL/
DIF
1
B3 B2 B1 B0
A2
Acquire
PD1 PD0
Zero filled
A1
A0
(LSB)
UNI/
BIP
B11 B10
Idle
SGL/
DIF
Zero filled
Acquire
PD1 PD0
CONV
B9 B8 B7 B6 B5 B4
Conversion
8
may vary in the
1
1
B11 B10
20 of 26
S
1
A2