IS43DR32800A-37CBL ISSI, IS43DR32800A-37CBL Datasheet - Page 12
IS43DR32800A-37CBL
Manufacturer Part Number
IS43DR32800A-37CBL
Description
DRAM 256M (8Mx32) 266MHz Commercial Temp
Manufacturer
ISSI
Datasheet
1.IS43DR32800A-37CBLI-TR.pdf
(41 pages)
Specifications of IS43DR32800A-37CBL
Product Category
DRAM
Rohs
yes
Factory Pack Quantity
162
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS43DR32800A-37CBL
Manufacturer:
ISSI
Quantity:
21
Company:
Part Number:
IS43DR32800A-37CBLI
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ISSI
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IS43DR32800A, IS43/46DR32801A
IDD Specifications & Test Conditions
12
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
Conditions
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);
CKE is HIGH, CS is HIGH between valid commands;
50% of Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS is HIGH between valid commands;
50% of Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle;
tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby current; All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge standby current; All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS is HIGH; Other control and 50% of address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
Active power-down current; All banks open;
tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Active standby current; All banks open;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and 50% of address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
50% of Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Integrated Silicon Solution, Inc. — www.issi.com
DDR2-
533C
-37C
130
165
280
55
70
20
60
8
DDR2-
400B
120
150
210
-5B
45
60
15
50
8
Units
mA
mA
mA
mA
mA
mA
mA
mA
09/08/2010
Rev. 00E