IS43DR32800A-37CBLI ISSI, IS43DR32800A-37CBLI Datasheet - Page 25

• Manufacturer Part Number: IS43DR32800A-37CBLI
• Description: DRAM 256M (8Mx32) 266MHz Industrial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-37CBLI

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 162

IS43DR32800A, IS43/46DR32801A
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed
in the mode register set.
34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800.
Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ‘tCK’ is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2,
even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and
these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian
distribution.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
Parameter
Clock period jitter
Clock period jitter during DLL locking
period
Cycle to cycle clock period jitter
Cycle to cycle clock period jitter during
DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles, n = 6 ...
10, inclusive
Cumulative error across n cycles, n = 11
... 50, inclusive
Duty cycle jitter
Symbol
tJIT(per)
tJIT(per,lck)
tJIT(cc
tJIT(cc,lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-
10per)
tERR(11-
50per)
tJIT(duty)
-100
-200
-160
-150
-175
-200
-200
-300
-450
-100
min
-80
DDR2-800
max
100
200
160
150
175
200
200
300
450
100
80
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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