SSTUF32864EHLF IDT, Integrated Device Technology Inc, SSTUF32864EHLF Datasheet - Page 8

• Manufacturer Part Number: SSTUF32864EHLF
• Description: IC REGIST BUFF 25BIT DDR2 96-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUF32864EHLF

• Logic Type: Configurable Registered Buffer for DDR2
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0987B—09/28/04
(over recommended operating free-air temperature range, unless otherwise noted)
Notes:
(over recommended operating free-air temperature range, unless otherwise noted)
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
Timing Requirements
SYMBOL
Switching Characteristics
SYMBOL
t
PDMSS
t
fmax
t
f
INACT
PARAMETER
t
PDM
clock
t
t
t
ACT
SU
t
phl
W
h
dV/dt_
1
dV/dt_r
dV/dt_f
2
Clock frequency
Pulse duration, CK, CK High or Low
Differential inputs active time (See notes 1 and 2)
Differential inputs inactive time (See notes 1 and 3)
Setup time
Setup time
Setup time
Hold time
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
CLK, CLK#
CLK, CLK#
RESET#
1
(Input)
From
PARAMETERS
MIN
1
1
V
DD
(Output)
= 1.8V ± 0.1V
To
Q
Q
Q
DCS before CK, CK ,
CSR high; CSR before
CK, CK , DCS high
DCS before CK, CK ,
CSR Low
DODT, DCKE and data
before CK, CK
PAR_IN before CK, CK
DCS, DODT, DCKE and
data after CK, CK
PAR_IN after CK, CK
MAX
4
4
1
1.41
MIN
335
V
DD
= 1.8V ±0.1V
8
TYP
MAX
UNIT
1.75
1.95
V/ns
V/ns
V/ns
3
0.50
0.50
MIN
0.7
0.5
0.5
1
UNITS
MHz
ns
ns
ns
ICSSSTUF32864A
MAX
335
10
15
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns