SSTUA32864BHLF IDT, Integrated Device Technology Inc, SSTUA32864BHLF Datasheet - Page 8

• Manufacturer Part Number: SSTUA32864BHLF
• Description: IC REGIST BUFFER 25BIT DDR 96BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUA32864BHLF

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.8V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1055A—01/28/05
(over recommended operating free-air temperature range, unless otherwise noted)
Notes:
(over recommended operating free-air temperature range, unless otherwise noted)
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
Timing Requirements
SYMBOL
Switching Characteristics
SYMBOL
t
PDMSS
t
fmax
t
f
INACT
PARAMETER
t
PDM
clock
t
t
t
ACT
SU
t
phl
W
h
dV/dt_∆
1
dV/dt_r
dV/dt_f
2
Clock frequency
Pulse duration, CK, CK High or Low
Differential inputs active time (See notes 1 and 2)
Differential inputs inactive time (See notes 1 and 3)
Setup time
Setup time
Hold time
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
CLK, CLK#
CLK, CLK#
RESET#
1
(Input)
From
PARAMETERS
MIN
1
1
V
DD
(Output)
= 1.8V ± 0.1V
To
Q
Q
Q
DCS before CK, CK↓,
CSR high; CSR before
CK, CK↓, DCS high
DCS before CK, CK↓,
CSR Low
DODT, DCKE and data
before CK, CK↓
DCS, DODT, DCKE and
data after CK, CK↓
PAR_IN after CK, CK↓
MAX
4
4
1
MIN
410
1.1
V
DD
= 1.8V ±0.1V
8
TYP
UNIT
MAX
V/ns
V/ns
V/ns
1.9
2
3
0.50
0.50
MIN
0.7
0.5
0.5
1
UNITS
MHz
ns
ns
ICSSSTUA32864B
MAX
410
10
15
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns