MAX1301AEUP+T Maxim Integrated, MAX1301AEUP+T Datasheet - Page 22

• Manufacturer Part Number: MAX1301AEUP+T
• Description: Analog to Digital Converters - ADC 16-Bit 4Ch 12V Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1301AEUP+T

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 130 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 91 dB
• Interface Type: Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

The MAX1300/MAX1301 contain one byte-wide mode-
control register. The timing diagram of Figure 15 shows
how to use the mode-control byte, and the mode-con-
trol byte format is shown in Table 7. The mode-control
byte is used to select the conversion method and to
control the power modes of the MAX1300/MAX1301.
8- and 4-Channel, ±3 x V
Serial 16-Bit ADCs
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or
Differential Input
Figure 14. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
22
______________________________________________________________________________________
FFFD
FFFD
FFFF
FFFE
8001
8000
7FFF
0003
0002
0001
0000
FFFF
FFFE
8001
8000
7FFF
0003
0002
0001
0000
(AGND1)
-32,768 -32,766
0
1
2
3
INPUT VOLTAGE (LSB [DECIMAL])
INPUT VOLTAGE (LSB [DECIMAL])
AGND1 (DIF/SGL = 0)
OV (DIF/SGL = 1)
-1
32,768
FSR
FSR
0
+1
1 LSB =
1 LSB =
65,536 x 4.096V
65,536 x 4.096V
FSR x V
FSR x V
Mode Control
+32,765 +32,767
65,533 65,535
REF
REF
REF
The conversion method is selected using the mode-con-
trol byte (see the Mode Control section), and the conver-
sion is initiated using a conversion-start command (Table
3, and Figures 2, 3, and 4).The MAX1300/MAX1301 con-
vert analog signals to digital data using one of three
methods:
•
•
•
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, -FSR to 0
External Clock Mode, Mode 0 (Figure 2)
• Highest maximum throughput (see the Electrical
• User controls the sample instant
• CS remains low during the conversion
• User supplies SCLK throughout the ADC con-
External Acquisition Mode, Mode 1 (Figure 3)
• Lowest maximum throughput (see the Electrical
• User controls the sample instant
• User supplies two bytes of SCLK, then drives
• After SSTRB transitions high, the user supplies
Internal Clock Mode, Mode 2 (Figure 4)
• High maximum throughput (see the Electrical
Characteristics table)
version and reads data at DOUT
Characteristics table)
CS high to relieve processor load while the ADC
converts
two bytes of SCLK and reads data at DOUT
Characteristics table)
FFFD
FFFF
FFFE
8001
8000
7FFF
0003
0002
0001
0000
Multirange Inputs,
0
1
2
3
Selecting the Conversion Method
INPUT VOLTAGE (LSB [DECIMAL])
32,768
FSR
1 LSB =
65,536 x 4.096V
FSR x V
65,533 65,535
REF
(AGND1)