SSTUAF32866BHLF IDT, Integrated Device Technology Inc, SSTUAF32866BHLF Datasheet - Page 12

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SSTUAF32866BHLF

Manufacturer Part Number
SSTUAF32866BHLF
Description
IC REGIST BUFF 25BIT DDR2 96-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of SSTUAF32866BHLF

Logic Type
1:2 Configurable Registered Buffer
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
25, 14
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
96-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTUAF32866BHLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
SSTUAF32866BHLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Terminal Functions
Terminal Name
CSR, DCS
Q1 - Q25
D1 - D25
PAR_IN
RESET
C0, C1
DODT
DCKE
QODT
QCKE
QERR
GND
V
QCS
PPO
CLK
CLK
V
Z
Z
REF
OH
DD
OL
Open Drain Output
Characteristics
Differential Input
Differential Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
LVCMOS Input
LVCMOS Input
Ground Input
1.8V nominal
0.9V nominal
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
Electrical
Input
Input
Ground
Power Supply Voltage
Input Reference Clock
Reserved for future use
Reserved for future use
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs
Asynchronous Reset Input. Resets registers and disables V
data and clock differential-input receivers.
Chip Select Inputs. Disables outputs D1 - D24 output switching
when both inputs are HIGH.
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
The outputs of this register bit will not be suspended by the DCS
and CSR controls
The outputs of this register bit will not be suspended by the DCS
and CSR controls
Data Outputs that are suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Partial Parity Output. Indicates off parity of D1 - D25
Parity Input arrives one cycle after corresponding data input
Output Error bit, generated one cycle after the corresponding data
output
12
Description
COMMERCIAL TEMPERATURE GRADE
ICSSSTUAF32866B
REF
7096/13

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