MAX1302AEUG+T Maxim Integrated, MAX1302AEUG+T Datasheet - Page 15

• Manufacturer Part Number: MAX1302AEUG+T
• Description: Analog to Digital Converters - ADC 16Bit, 8Ch, 4.096V Multi-In Serial ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1302AEUG+T

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 115 kSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 1111.1 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 2. External Clock-Mode Conversion (Mode 0)
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±V
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±V
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
SSTRB
TRACK AND HOLD*
DOUT
SCLK
DIN
CS
ANALOG INPUT
IMPEDANCE
HIGH
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
S
HOLD
C2
______________________________________________________________________________________
C1
C0
0
BYTE 1
0
8-Channel, ±V
0
0
TRACK
t
ACQ
REF
REF
BYTE 2
range
dif-
f
SAMPLE
≈ f
SAMPLING INSTANT
SCLK
/ 32
The MAX1302 input-tracking circuitry has a 1.5MHz
small-signal bandwidth. The 1.5MHz input bandwidth
makes it possible to digitize high-speed transient events.
Harmonic distortion increases when digitizing signal fre-
quencies above 15kHz as shown in the -SFDR, THD vs.
Analog Input Frequency plot in the Typical Operating
Characteristics .
Figure 7 illustrates the software-selectable single-
ended analog input voltage range that produces a valid
digital output. Each analog input channel can be inde-
pendently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
B15
REF
B14
Analog Input Range and Fault Tolerance
B13
B12
BYTE 3
Multirange Inputs,
B11
Serial 16-Bit ADC
B10
B9
HOLD
B8
B7
Analog Input Bandwidth
B6
B5
B4
BYTE 4
B3
B2
B1
B0
IMPEDANCE
HIGH
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