M4A5-64/32-7VNI Lattice, M4A5-64/32-7VNI Datasheet - Page 6
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M4A5-64/32-7VNI
Manufacturer Part Number
M4A5-64/32-7VNI
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A5-64/32-7VNI
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
125 MHz
Delay Time
5 ns
Number Of Programmable I/os
900
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
800
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-64/32-7VNI
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
M4A5-64/32-7VNI48
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells
internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through
the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate
with each other with consistent, predictable delays.
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on
a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single
programmable device; the software partitions the design into PAL blocks through the central switch matrix
so that the designer does not have to be concerned with the internal architecture of the device.
Each PAL block consists of:
◆
◆
◆
◆
◆
◆
◆
Notes:
1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
6
Product-term array
Logic allocator
Macrocells
Output switch matrix
I/O cells
Input switch matrix
Clock generator
Macrocell-I/O Cell Ratio
Input Switch Matrix
Input Registers
Central Switch Matrix
Output Switch Matrix
Table 4. Architectural Summary of ispMACH 4A devices
M4A3-256/128, M4A5-256/128
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
ispMACH 4A Family
M4A3-384
M4A3-512
2:1
Yes
Yes
Yes
Yes
ispMACH 4A Devices
M4A3-256/160
M4A3-256/192
M4A3-32/32
M4A5-32/32
M4A3-64/64
Yes
1:1
Yes
Yes
No
1