M4A5-64/32-7JNI Lattice, M4A5-64/32-7JNI Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
M4A5-64/32-7JNI
Manufacturer Part Number
M4A5-64/32-7JNI
Description
CPLD - Complex Programmable Logic Devices 64 MC 32 IO JTAG ISP 5V 7.5ns
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A5-64/32-7JNI
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
182 MHz
Delay Time
7.5 ns
Number Of Programmable I/os
32
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
PLCC-44
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
780
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-64/32-7JNI
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
e. T-type with programmable T polarity
c. Latch with XOR
a. D-type with XOR
L
T
G
D
AP AR
AP AR
AP AR
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
Q
Q
Q
ispMACH 4A Family
b. D-type with programmable D polarity
d. Latch with programmable D polarity
f. Combinatorial with XOR
D
L
G
AP AR
AP AR
Q
Q
17466G-011
11