MAX1464CAI+T Maxim Integrated, MAX1464CAI+T Datasheet - Page 42

• Manufacturer Part Number: MAX1464CAI+T
• Description: Digital Signal Processors & Controllers - DSP, DSC Low-Power Low-Noise Multichannel Sensor Signal Processor
• Manufacturer: Maxim Integrated
• Series: MAX1464r

Specifications of MAX1464CAI+T

• Data Bus Width: 16 bit
• Program Memory Size: 4 KB, 128 B
• Maximum Clock Frequency: 5.3 MHz
• Number Of Programmable I/os: 2
• Operating Supply Voltage: 5 V
• Interface Type: SPI
• On-chip Adc: Yes
• Processor Series: MAX1464
• Product: DSPs
• Program Memory Type: Flash

Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Table 39. Command Register (CR) Decoding
Table 38. Internal Register Set Address
(IRSA) Decoding
42
Note 17: Reading and writing the CPU ports by the serial interface is allowed while the CPU is executing its program. In the case of
1010–1110
IRSA[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CR
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
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simultaneous access of the ports by both the CPU and the serial interface, the CPU has priority. Although this procedure is
allowed, it is not recommended, as the serial interface may change values previously written by the CPU. If a “snapshot”
of the ports and module register contents is required while the CPU is running, halt the CPU, read the contents of the ports
and/or module registers, and restore the original port/module register values prior to starting the CPU again.
Write 16-bit DHR contents into the CPU port specified by PFAR[3:0].
Write 8-bit DHR[7:0] contents into FLASH memory location specified by PFAR[11:0].
Read 16-bit CPU port specified by PFAR[3:0] into DHR.
Read 8-bit FLASH location specified by PFAR[11:0] into DHR[7:0].
Read 16-bit CPU accumulator register (A) into DHR.
Read 8-bit FLASH location specified by the CPU program counter (PC) (CPU instruction or data) to
DHR[7:0].
Read 16-bit CPU PC to DHR.
Halt the CPU.
Start the CPU, i.e., clear the HALT CPU bit from the current PC location.
Single step the CPU. Only one CPU clock cycle is executed.
Reset the PC to zero.
Reset the modules, FLASH controller, and CPU registers D, E, F.
No operation.
Erase a 64-byte “page” of FLASH as specified by PFAR[11:6].
Erase the entire FLASH partition (4kB, PS0, or 128 bytes, PS1).
Change from FLASH partition PS0 to FLASH partition PS1 (128 byte auxiliary). A subsequent halt
CPU command resets the partition selection back to PS0.
ADDRESSED
PFAR[15:12]
DHR[15:12]
REGISTER
PFAR[11:8]
DHR[11:8]
PFAR[3:0]
PFAR[7:4]
DHR[3:0]
DHR[7:4]
IMR[3:0]
NIBBLE
CR[3:0]
—
Write IRSD[3:0] to DHR[11:8].
Write IRSD[3:0] to DHR[15:12].
Write IRSD[3:0] to PFAR[3:0].
Write IRSD[3:0] to PFAR[7:4].
Write IRSD[3:0] to PFAR[11:8].
Write IRSD[3:0] to PFAR[15:12].
Write IRSD[3:0] to CR[3:0].
Write IRSD[3:0] to IR[3:0].
Unused.
Write IRSD[3:0] to DHR[3:0].
Write IRSD[3:0] to DHR[7:4].
DESCRIPTION
DESCRIPTION
CPU HALTED
No (Note 17)
No (Note 17)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
—