dsPIC33FJ06GS001-I/P Microchip Technology, dsPIC33FJ06GS001-I/P Datasheet
dsPIC33FJ06GS001-I/P
Specifications of dsPIC33FJ06GS001-I/P
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dsPIC33FJ06GS001-I/P Summary of contents
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... Customers using only one of these devices should use development tools that already provide support for device programming ...
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... P = Power and this document comply with this program memory word can be © 2011 Microchip Technology Inc. ...
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... TABLE 2-2: CODE MEMORY SIZE User Memory dsPIC33F Device Address Limit (Instruction Words) dsPIC33FJ16GP101 0x002BFA (5.6K) dsPIC33FJ16GP102 0x002BFA (5.6K) dsPIC33FJ16MC101 0x002BFA (5.6K) dsPIC33FJ16MC102 0x002BFA (5.6K) dsPIC33FJ06GS001 0x00FEE (2K) dsPIC33FJ06GS101A 0x00FEE (2K) dsPIC33FJ06GS102A 0x00FEE (2K) dsPIC33FJ06GS202A 0x00FEE (2K) dsPIC33FJ09GS302 0x017EE (3K) dsPIC33FJ16GP101 0x002BFA (5.6K) © 2011 Microchip Technology Inc. FIGURE 2-2: Executive Code Memory Section 7 ...
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... Legend: — = unimplemented, read as ‘1’. Note 1: This address applies to dsPIC33FJ06GS001 and dsPIC33FJ06GSX0XA Configuration bits. 2: This address applies to dsPIC33FJ09GS302 Configuration bits. 3: This bit is reserved for use by development tools and must be programmed as ‘1’. 4: This bit is reserved; program as ‘0’. ...
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... Microchip Technology Inc imperative that both GWRP and GCP are ‘1’ while the device is being programmed and verified. Only after the device is programmed and verified should either GWRP or GCP be programmed to ‘ ...
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... Then, program the code-protect Configuration bits, if required. FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ Perform Bulk Erase Program Memory and Configuration Words Verify Program Memory and Configuration Words Program Code-protect Configuration Bits Exit ICSP End © 2011 Microchip Technology Inc. ...
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... PGEDx b31 b30 PGECx P18 © 2011 Microchip Technology Inc. The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily hexadecimal). The device will enter Program/Verify (1) mode only if the sequence is valid. The Most Significant ...
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... CPU). See Figure 3-4 for details P4a MSB Execute 24-bit Instruction, Fetch Next Control Code P4a MSB Execute 24-bit Instruction, Fetch Next Control Code © 2011 Microchip Technology Inc ...
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... Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGEDx = Input © 2011 Microchip Technology Inc. The REGOUT code is unique because the PGEDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGEDx pin becomes an output as the VISI register is shifted out ...
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... All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle write operation has been completed. Starting a programming cycle is performed as follows: BSET for detailed STARTING AND STOPPING A PROGRAMMING CYCLE NVMCON, #WR © 2011 Microchip Technology Inc. ...
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... Memory word program Note 1: These bits can only be reset on a Power-on Reset (POR). 2: All other combinations of NVMOP<3:0> are unimplemented. 3: This command will erase either all of program memory or all of executive memory, but not both. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...
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... Set the WR bit to Initiate Erase Description 0x200 0x200 #0x404F, W10 W10, NVMCON #0x00, W1 W1, TBLPAG NVMCON, #WR Section 9.0 “AC/DC Characteristics and Requirements”) to allow sufficient time for the Bulk Erase operation to PROGRAM MEMORY ERASE FLOW Start Delay P11 + P10 Time End © 2011 Microchip Technology Inc. ...
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... Step 5: Load the lower instruction word to the W5 register and the upper instruction byte to the W6 register. 0000 2xxxx5 MOV 0000 200xx6 MOV © 2011 Microchip Technology Inc. FIGURE 3-7: PROGRAM CODE MEMORY FLOW Load Lower Word and Upper Byte of instruction to Write Latch and ...
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... GOTO 0000 000000 NOP — — Repeat until the WR bit is clear. Step 9: Repeat steps 5-8 to write the remaining program words. DS70659B-page 14 Description W5, [W2] W6, [W2++] NVMCON, #WR Section 9.0 “AC/DC Characteristics and Timing NVMCON, W0 W0, VISI 0x200 © 2011 Microchip Technology Inc. ...
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... NOP 0000 000000 NOP © 2011 Microchip Technology Inc. Table 3-6 shows the ICSP programming details for writing the Configuration bits. In order to verify the data by reading the Configuration bits after performing the write, the code protection bits should initially be programmed to a ‘1’ to ensure that the verification can be performed properly ...
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... Clock out contents of VISI register. 0001 <VISI> 0000 040200 GOTO 0000 000000 NOP — — Repeat until the WR bit is clear. Step 9: Repeat steps 5-8 to write the remaining Configuration bits. DS70659B-page 16 Description Section 9.0 “AC/DC Characteristics and Timing NVMCON, W0 W0, VISI 0x200 © 2011 Microchip Technology Inc. ...
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... NOP 0000 BA1BB6 TBLRDL 0000 000000 NOP 0000 000000 NOP © 2011 Microchip Technology Inc. To minimize programming time, the same packed data format that the programming executive uses is utilized. See Section 6.2 Commands” format. Description 0x200 0x200 <Address7:0>, W0 W0, TBLPAG #< ...
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... MOV W5, VISI 0000 000000 NOP Clock out contents of VISI register. 0001 <VISI> 0000 000000 NOP Step 5: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 6: Repeat step 3-5 until all desired code memory is read. DS70659B-page 18 Description 0x200 © 2011 Microchip Technology Inc. ...
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... NOP Step 4: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 5: Repeat step 3-4 to read remaining Configuration bits. © 2011 Microchip Technology Inc. Table 3-8 shows the ICSP programming details for reading the Configuration bits. Description 0x200 0x200 <Address7:0>, W0 W0, TBLPAG <Address15:0>, W6 ...
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... PGECx and PGEDx before removing V 3-8. The lower FIGURE 3-9: Memory” for MCLR V DD PGEDx PGECx Failure Report Error IH Figure 3-9. The only . IH EXITING ICSP™ MODE P16 P17 PGEDx = Input © 2011 Microchip Technology Inc. ...
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... RAM for variable storage and program execution. After running the programming executive, assumptions should be made about the contents of data RAM. © 2011 Microchip Technology Inc. 4.1 Overview of the Programming Process Figure 4-1 shows the high-level overview of the pro- gramming process. First, it must be determined if the programming executive is present in executive mem- ory, and then Enhanced ICSP mode is entered ...
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... Yes Exit ICSP Mode Enter Enhanced ICSP Mode Sanity Check End Note 1: See TABLE 7-1: “Device IDs and Revision” for the Application ID of each device. CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE No (1) Prog. Executive must be Programmed © 2011 Microchip Technology Inc. ...
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... Step 3: Output the VISI register using the REGOUT command. Clock out contents of the VISI register. 0001 <VISI> © 2011 Microchip Technology Inc. After the programmer has clocked out the Application ID Word, it must be inspected. If the application ID has the value listed in sion”, the programming executive is resident in mem- ...
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... determined that the device is not blank, it must be erased before attempting to program the chip. must be IH Program/Verify Entry Code = 0x4D434850 ... b29 b28 b27 P1A P1B · P19 © 2011 Microchip Technology Inc. ...
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... Is PROGW response PASS? Yes RemainingCmds = RemainingCmds – 1 BaseAddress = BaseAddress + 0x02 Is No RemainingCmds ‘0’? Yes End © 2011 Microchip Technology Inc. FIGURE 4-5: for a full BaseAddress = BaseAddress + 0x80 No Failure Report Error FLOWCHART FOR MULTIPLE WORD PROGRAMMING Start BaseAddress = 0x0 RemainingCmds = 87 Send PROGW ...
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... PGECx and PGEDx before removing V FIGURE 4-7: No MCLR V DD PGEDx PGECx Failure Report Error for more IH Figure 4-7. The only . IH EXITING ENHANCED ICSP™ MODE P16 P17 PGEDx = Input © 2011 Microchip Technology Inc. ...
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... Memory Program the Programming Executive Read/Verify the Programming Executive Exit ICSP mode End © 2011 Microchip Technology Inc. 5.2 Erasing Executive Memory The procedure for erasing executive memory is similar to that of erasing program memory and is shown in Figure 5-2. It consists of setting NVMCON to 0x404F, initializing the TBLPAG register to the beginning of executive memory ...
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... Step 5: Wait for Bulk Erase operation to complete and make sure the WR bit is clear. — — Externally time ‘P11’ ms (see Requirements”) to allow sufficient time for the Bulk Erase operation to complete. DS70659B-page 28 Description 0x200 0x200 #0x404F, W10 W10, NVMCON #0x80, W1 W1, TBLPAG NVMCON, #WR Section 9.0 “AC/DC Characteristics and Timing © 2011 Microchip Technology Inc. ...
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... NOP 0000 880191 MOV Step 4: Initialize the write pointer (W2) for the TBLWT instruction. 0000 2xxxx2 MOV © 2011 Microchip Technology Inc. FIGURE 5-3: PROGRAM CODE MEMORY FLOW Load Lower Word and Upper Byte of instruction to Write Latch and increment the Write Pointer Start Write Sequence ...
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... GOTO 0000 000000 NOP — — Repeat until the WR bit is clear. Step 9: Repeat steps 5-8 to write the remaining executive memory words. DS70659B-page 30 Description #<LOW_WORD>, W5 #<HIGH_BYTE>, W6 W5, [W2] W6, [W2++] NVMCON, #WR Section 9.0 “AC/DC Characteristics and Timing NVMCON, W0 W0, VISI 0x200 © 2011 Microchip Technology Inc. ...
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... NOP 0000 BA1BB6 TBLRDL 0000 000000 NOP 0000 000000 NOP © 2011 Microchip Technology Inc. To minimize programming time, the same packed data format that the programming executive uses is utilized. See Section 6.2 Commands” format. Description 0x200 0x200 #0x80, W0 W0, TBLPAG #< ...
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... MOV W5, VISI 0000 000000 NOP Clock out contents of VISI register. 0001 <VISI> 0000 000000 NOP Step 5: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 6: Repeat step 3-5 until all desired executive memory is read. DS70659B-page 32 Description 0x200 © 2011 Microchip Technology Inc. ...
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... Refer to Section 5.4 “Reading Executive Memory” implementation details of reading executive memory. © 2011 Microchip Technology Inc. FIGURE 5-4: 5-4. The lower for No ...
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... P9a P9b PGECx = Input (Idle) PGEDx = Output PROGRAMMING EXECUTIVE SERIAL TIMING ... LSb Figure 6-2. Host Clocks Out Response MSB LSB PGECx = Input PGEDx = Output © 2011 Microchip Technology Inc. ...
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... QVER 0xC 5 CRCP 0xD 4 PROGW 0xE 5 QBLANK © 2011 Microchip Technology Inc safety measure, the programmer should use the command time outs identified in command time out expires, the programmer should reset the flow control programming the device again. described in Time Out 1 ms Sanity check ...
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... PACKED DATA FORMAT Figure 6-4. This PACKED INSTRUCTION WORD FORMAT 8 7 LSW1 MSB1 LSW2 When the number of instruction words transferred is odd, MSB2 is zero and LSW2 cannot be transmitted. PROGRAMMING EXECUTIVE ERROR HANDLING executive will “NACK” Section 6.3.1.3 “QE_Code © 2011 Microchip Technology Inc. 0 all ...
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... This command is used as a “Sanity Check” to verify that the programming executive is operational. Expected Response (2 words): 0x1000 0x0002 Note: This instruction is not required for programming, but is development purposes only. © 2011 Microchip Technology Inc. 6.2.4 Opcode 0 Field Opcode Length N Addr_MSB Addr_LS ...
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... After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1500 0x0002 Note: Refer to Table 2-2 information. © 2011 Microchip Technology Inc Length Addr_MSB ... Description Figure 6-4. for code memory size ...
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... The ERASEP command instructs the programming executive to page erase [NUM_PAGES] of code mem- ory. The code memory must be erased at an “even” 512 instruction word address boundary Expected Response (2 words): 0x1900 0x0002 © 2011 Microchip Technology Inc. 6.2.4.6 QVER Command Opcode ...
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... After the word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1D00 0x0002 Least Length Addr_MSB Addr_LS Data_LS Description © 2011 Microchip Technology Inc. ...
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... Expected Response (2 words for non-blank device): 0x1E0F 0x0002 Note: Ensure that the address range selected excludes the configuration bytes at the top of memory when using the QBLANK com- mand; otherwise, a non-blank response will be generated. © 2011 Microchip Technology Inc. 0 DS70659B-page 41 ...
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... D_N (if applicable) Description Response opcode. Programmer command that generated the response. Query code or error code. Response length in 16-bit words (includes 2 header words). First 16-bit data word (if applicable). Last 16-bit data word (if applicable). Table 6-2). If the command was © 2011 Microchip Technology Inc. ...
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... Code memory is blank 0xMN, where programming executive QVER software version = M.N (i.e., 0x32 means software version 3.2) © 2011 Microchip Technology Inc. When the programming executive processes any command other than a Query, the QE_Code represents an error code. Supported error codes are shown in Table ...
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... Table 7-1 lists the identification information for each device. Table 7-2 shows the Device ID registers. TABLE 7-1: DEVICE IDs AND REVISION Device DEVID Register Value dsPIC33FJ16GP101 dsPIC33FJ16GP102 dsPIC33FJ16MC101 dsPIC33FJ16MC102 dsPIC33FJ06GS001 dsPIC33FJ06GS101A dsPIC33FJ06GS102A dsPIC33FJ06GS202A dsPIC33FJ09GS302 TABLE 7-2: DEVICE ID REGISTERS Address Name 15 0xFF0000 DEVID 0xFF0002 DEVREV ...
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... Table 8-3 describes the configuration bit masks for the dsPIC33FJ06GS001, dsPIC33FJ06GSX0XA, dsPIC33FJ09GS302 devices. TABLE 8-3: dsPIC33FJ06GS001, dsPIC33FJ06GSX0XA, AND dsPIC33FJ09GS302 CONFIGURATION BIT MASKS Device FICD dsPIC33FJ06GS001 0xA3 dsPIC33FJ06GS101A 0xA3 dsPIC33FJ06GS102A 0xA3 dsPIC33FJ06GS202A 0xA3 dsPIC33FJ09GS302 0xA3 © 2011 Microchip Technology Inc. ...
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... Normal programming μA — mA — mA — V — V — 3. 3. meet AC specifications ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — ms — μs — μs — should always be within SS © 2011 Microchip Technology Inc. ...
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... Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to the “Electrical Characteristics” section in the specific device data sheet. 3: This time applies to both Program Memory words and Configuration words. © 2011 Microchip Technology Inc. Min. Max. ...
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... DEVICES WITH VOLATILE CONFIGURATION BITS NOTES: DS70659B-page 48 © 2011 Microchip Technology Inc. ...
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... CC – two-digit hexadecimal checksum that is the two’s complement of the sum of all the preceding bytes in the line record. © 2011 Microchip Technology Inc. Because the Intel hex file format is byte-oriented, and the 16-bit program counter is not, program memory sections require special treatment. Each 24-bit pro- gram word is extended to 32 bits by inserting a so-called “ ...
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... Updated the the following AD/DC Characteristics and Timing Requirements (see Table - Maximum value for parameter D113 was changed - Added parameter D114 - Maximum value and conditions for parameter D80 were changed - Minimum value and conditions for parameter D90 were changed DS70659B-page 50 Table 8-1) 9-1) © 2011 Microchip Technology Inc. ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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... Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2011 Microchip Technology Inc. 05/02/11 ...