dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 126

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
8.1
The
dsPIC33FJ32(GP/MC)101/102/104 devices provide
seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with 4x PLL
• Primary (MS, HS or EC) Oscillator
• Primary Oscillator with 4x PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
8.1.1
8.1.1.1
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The FRC frequency depends on the FRC accuracy
(see
Tuning register (see
8.1.1.2
The primary oscillator can use one of the following as
its clock source:
• MS (Crystal): Crystals and ceramic resonators in
• HS (High-Speed Crystal): Crystals in the range of
• EC (External Clock): The external clock signal is
8.1.1.3
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
DS70652E-page 126
the range of 4 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
10 MHz to 32 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
directly applied to the OSC1 pin.
Table
CPU Clocking System
dsPIC33FJ16(GP/MC)101/102
26-18) and the value of the FRC Oscillator
SYSTEM CLOCK SOURCES
Fast RC
Primary
Secondary
Register
8-3).
and
8.1.1.4
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
8.1.1.5
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip, 4x
Phase Lock Loop (PLL) to provide faster output
frequencies for device operation. PLL configuration is
described in
8.1.2
The oscillator source used at a device Power-on
Reset event is selected using Configuration bit
settings. The Oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to
Bits”
Selection
(FOSCSEL<2:0>), and the Primary Oscillator Mode
Select
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. The FRC primary oscillator is
the default (unprogrammed) selection.
The Configuration bits allow users to choose among
12 different clock modes, shown in
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) F
generate the device instruction clock (F
peripheral clock time base (F
operating speed of the device, and speeds up to
16 MHz are supported by the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
architecture.
Instruction execution speed or device operating
frequency, F
EQUATION 8-1:
for further details.) The initial Oscillator
Configuration
SYSTEM CLOCK SELECTION
CY
Section 8.1.3 “PLL
Low-Power RC
PLL
Configuration
, is given by:
 2011-2012 Microchip Technology Inc.
F
CY
DEVICE OPERATING
FREQUENCY
Section 23.1 “Configuration
=
F
-------------
bits,
OSC
2
bits,
P
Configuration”.
OSC
). F
Table
is divided by 2 to
CY
POSCMD<1:0>
FNOSC<2:0>
8-1.
CY
defines the
) and the