ispLSI 2128A-80LT176I Lattice, ispLSI 2128A-80LT176I Datasheet - Page 7

• Manufacturer Part Number: ispLSI 2128A-80LT176I
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 2128A-80LT176I

• Memory Type: EEPROM
• Number Of Macrocells: 128
• Maximum Operating Frequency: 83 MHz
• Delay Time: 18.5 ns
• Number Of Programmable I/os: 128
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-176
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 200
• Supply Current: 165 mA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Derivations of
Note: Calculations are based upon timing specifications for the ispLSI 2128/A-100L.
GOE0, 1
Ded. In
Y0,1,2
ispLSI 2128/A Timing Model
I/O Pin
Reset
(Input)
t
t
t
12.6 ns
su
h
co
4.4 ns
3.8 ns
=
=
=
=
=
=
=
=
=
=
=
=
Logic + Reg su - Clock (min)
(
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.5 + 1.7 + 7.3) + (1.2) + (0.5 + 1.7 + 4.1)
Clock (max) + Reg h - Logic
(
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.5 + 1.7 + 7.1) + ( 4.0) + (0.5 + 1.7 + 7.3)
Clock (max) + Reg co + Output
(
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.5 + 1.7 + 7.1) + (0.3) + (1.4 + 1.6)
t
t
t
I/O Delay
io +
io +
io +
#21
#20
t
I/O Cell
su,
t
t
t
grp +
grp +
grp +
t
h and
t
t
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
t
co from the Product Term Clock
#45
#43, 44
#42
t
GRP
GRP
#22
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
t
orp +
t
grp +
t
grp +
Reg 4 PT Bypass
XOR Delays
#33 - 35
t
Table 2-0042/2128
Control
PTs
Feedback
ob)
#25 - 27
t
20 PT
ptck(min))
t
#24
20ptxor)
Comb 4 PT Bypass #23
7
OE
RE
CK
Specifications ispLSI 2128/A
GLB
GLB Reg Bypass
D
RST
GLB Reg
#29 - 32
Delay
#28
Q
ORP Bypass
0491
Delay
ORP
ORP
#37
#36
#40, 41
#38,
39
I/O Cell
(Output)
I/O Pin