ispLSI 2096A-80LT128I Lattice, ispLSI 2096A-80LT128I Datasheet - Page 9

• Manufacturer Part Number: ispLSI 2096A-80LT128I
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 2096A-80LT128I

• Memory Type: EEPROM
• Number Of Macrocells: 96
• Maximum Operating Frequency: 83 MHz
• Delay Time: 18.5 ns
• Number Of Programmable I/os: 96
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-128
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 150 mA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Pin Description
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
GOE 0, GOE 1
IN 2, IN 4, IN 5
ispEN
SDI/IN 0
MODE/IN 1
SDO
SCLK/IN 3
RESET
Y0, Y1, Y2
GND
VCC
NC
1
NAME
2
2
2
104,
117,
123,
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
64,
51,
18
20
46
50
78
19
15
97,
16,
14,
2,
8,
1,
PQFP & TQFP PIN NUMBERS
105,
118,
124,
114
112
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
84,
17,
48,
47,
83,
3,
9,
100,
106,
119,
125,
110
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
10,
33,
82,
79,
80
4,
101,
107,
120,
126,
111,
113
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
11,
49,
5,
102,
108,
121,
127,
115,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
12,
65,
6,
103
109
122
128
116
81,
26
32
39
45
57
63
71
77
90
96
13
7
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enables input pins.
Dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN0 also is used as one of the two control pins for the isp state
machine. When ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the isp state machine.
When ispEN is high, it functions as a dedicated input pin.
Output - When ispEN is logic low, it functions as an output pin to read
serial shift register data.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
Ground (GND)
V
No Connect.
9
CC
Specifications ispLSI 2096/A
DESCRIPTION
Table 2-0002-2096