ispLSI 2032A-80LT48I Lattice, ispLSI 2032A-80LT48I Datasheet
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ispLSI 2032A-80LT48I
Specifications of ispLSI 2032A-80LT48I
Related parts for ispLSI 2032A-80LT48I
ispLSI 2032A-80LT48I Summary of contents
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... Features • ENHANCEMENTS — ispLSI 2032A is Fully Form and Function Compatible to the ispLSI 2032, with Identical Timing Specifcations and Packaging — ispLSI 2032A is Built on an Advanced 0.35 Micron 2 ® E CMOS Technology • HIGH DENSITY PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — ...
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Functional Block Diagram Figure 1. ispLSI 2032/A Functional Block Diagram GOE 0 I I/O 2 I/O 3 I I/O 6 I/O 7 I/O 8 I I/O 11 I/O ...
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Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C ...
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... Typical values are and T = 25° Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 2032/A Figure 2 ...
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External Timing Parameters 4 TEST 2 PARAMETER # COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Prop. Delay Clk Frequency with Internal Feedback max f – 4 Clk ...
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External Timing Parameters 4 TEST 2 PARAMETER # COND. t pd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock ...
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Internal Timing Parameters Over Recommended Operating Conditions 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc ...
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Internal Timing Parameters 2 PARAMETER # Inputs Input Buffer Delay t 21 Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 #42 GOE Derivations of su, h and co from the Product Term Clock ...
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Power Consumption Power consumption in the ispLSI 2032 and 2032A de- vices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax 120 ...
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Pin Description 44-PIN PLCC PIN NUMBERS NAME I I/O 3 15, 16, 17, 18, I I/O 7 22, 19, 20, 21, I I/O 11 25, 26, 27, 28, I I/O 15 29, ...
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Pin Configuration ispLSI 2032/A 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I VCC ispEN 1 SDI/IN 0 I/O 0 I Pins have dual function capability. ispLSI 2032/A 44-Pin TQFP Pinout Diagram ...
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Pin Configuration ispLSI 2032/A 48-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 VCC ispEN 2 SDI/IN 0 I/O 0 I pins are not to be connected to any active signal, ...
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... INDUSTRIAL ispLSI 2032A-80LJ44I 1 5 ispLSI 2032A-80LT44I 1 5 ispLSI 2032A-80LT48I 14 Grade Blank = Commercial I = Industrial Package J = PLCC T44 = TQFP T48 = TQFP JN = Lead-Free PLCC TN48 = Lead-Free TQFP TN48 = Lead-Free TQFP Power L = Low ...
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... ORDERING NUMBER ispLSI 2032A-180LJN44 ispLSI 2032A-180LTN44 ispLSI 2032A-180LTN48 ispLSI 2032A-150LJN44 ispLSI 2032A-150LTN44 ispLSI 2032A-150LTN48 ispLSI 2032A-135LJN44 ispLSI 2032A-135LTN44 ispLSI 2032A-135LTN48 1 0 ispLSI 2032A-110LJN44 1 0 ispLSI 2032A-110LTN44 1 0 ispLSI 2032A-110LTN48 1 5 ispLSI 2032A-80LJN44 ...
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... ispLSI 2032A-80LJN44I 1 5 ispLSI 2032A-80LTN44I 1 5 ispLSI 2032A-80LTN48I Change Summary Previous Lattice release. Updated for lead-free package options Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP Lead-Free 48-Pin TQFP ...