ispLSI 1032E-125LJ Lattice, ispLSI 1032E-125LJ Datasheet - Page 13

• Manufacturer Part Number: ispLSI 1032E-125LJ
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 1032E-125LJ

• Memory Type: EEPROM
• Number Of Macrocells: 128
• Maximum Operating Frequency: 167 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-84
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 190 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

Pin Description
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
RESET
Y0
Y1
Y2
Y3
NC
GND
V
ispEN
SDI/IN 0
MODE/IN 1
SDO/IN 2
SCLK/IN 3
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
IN 4 - IN 7
CC
2
Name
1
1
1
1
CPGA Pin Numbers
G1
E1
E11
G9
G11
G3
C6,
F2,
G3
G2
K6
J7
G10
F1,
K1,
K3,
L4,
L7,
K8,
L11,
J11,
E9,
B11, C10, A11, B10,
B9,
A8,
A5,
B4,
A1,
C1,
E10, C7,
F3,
F11
H1,
J2,
L2,
J5,
K7,
L9,
K10, J10,
H10, H11, F10,
D11, D10, C11,
A10, A9,
B6,
B5,
A3,
B2,
D2,
F9,
H2,
L1,
L3,
K5,
L6,
L10,
B7,
C5,
A2,
C2,
D1,
A6,
J6
J1,
K2,
K4,
L5,
L8,
K9,
K11,
B8,
A7,
A4,
B3,
B1,
E3
E2
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
No Connect
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Ground (GND)
V
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Dedicated input pins to the device.
CC
12
Specifications ispLSI 1032
Description
Table 2-0002-32/883