ispLSI 2096A-125LT128 Lattice, ispLSI 2096A-125LT128 Datasheet - Page 2

• Manufacturer Part Number: ispLSI 2096A-125LT128
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 2096A-125LT128

• Memory Type: EEPROM
• Number Of Macrocells: 96
• Maximum Operating Frequency: 125 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 96
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-128
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 295 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

Figure 1. ispLSI 2096/A Functional Block Diagram
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096 and 2096A device contains three Megablocks.
MODE/IN 1
Functional Block Diagram
SDI/IN 0
RESET
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
SDO
A0
A1
A2
A3
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
Routing
Global
(GRP)
Pool
2
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096 and 2096A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Specifications ispLSI 2096/A
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
B7
B6
B5
B4
0917
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48