MAX159BCUA+T Maxim Integrated, MAX159BCUA+T Datasheet - Page 11

• Manufacturer Part Number: MAX159BCUA+T
• Description: Analog to Digital Converters - ADC 10-Bit 108ksps 5.25V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX159BCUA+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 108 KSPs
• Resolution: 10 bit
• Input Type: Pseudo-Differential
• Snr: No
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 727 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 5.25 V

Table 1. Serial Output Data Stream for Internal and External Clock Mode
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise (which includes all
spectral components minus the fundamental), the first
five harmonics, and the DC offset.
Signal-to-noise plus distortion is the ratio of the funda-
mental input frequency’s RMS amplitude to RMS equiv-
alent of all other ADC output signals:
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the effective number of bits as follows:
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V
V
monics.
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
The MAX157/MAX159 interface is fully compatible with
SPI/QSPI and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
DOUT (Internal Clock)
DOUT (External Clock)
5
SINAD(dB) = 20
THD = 20
are the amplitudes of the 2nd through 5th-order har-
Signal-to-Noise Plus Distortion (SINAD)
Spurious-Free Dynamic Range (SFDR)
SCLK CYCLE
1
is the fundamental amplitude and V
Connection to Standard Interfaces
ENOB = (SINAD - 1.76) / 6.02
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
log
______________________________________________________________________________________
log
V
2 2
(Noise + Distortion)
+ V
EOC
1
1
3 2
Signal
V
+ V
1 2
2
1
1
4 2
RMS
+ V
3
1
1
5 2
CHID
CHID
RMS
2
+2.7V, Low-Power, 2-Channel,
4
through
D9
D9
5
D8
D8
6
serial clock for the MAX157/MAX159. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
2) Wait for the minimum wake-up time (t
3) Activate SCLK for a minimum of 16 clock cycles. The
4) Pull CS/SHDN high at or after the 16th falling clock
5) With CS/SHDN high, wait at least 60ns (t
Data can be output either in two 8-bit sequences or
continuously. The bytes will contain the result of the
conversion padded with three leading ones, the chan-
nel identification before the MSB, and two trailing sub-
bits. If the serial clock hasn’t been idled after the last
sub-bit (S0) and CS/SHDN is kept low, DOUT sends
trailing zeros.
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c). Two
consecutive 8-bit readings are necessary to obtain the
entire 10-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
µP on SCLK’s rising edge. The first 8-bit data stream
contains three leading ones, followed by channel identi-
fication and the first four data bits starting with the MSB.
The second 8-bit data stream contains the remaining
bits, D5 through D0, and the sub-bits S1 and S0.
D7
D7
7
CS/SHDN low while SCLK is low.
fied before activating SCLK.
first falling clock edge will generate a serial data-
stream of three leading ones, followed by the chan-
nel identification, the MSB of the digitized input
signal, and two sub-bits. DOUT transitions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing char-
acteristic. Data should be clocked into the µP on
SCLK’s rising edge.
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the sub-bits.
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
D6
D6
8
D5
D5
9
SPI and MICROWIRE Interface
D4
D4
10
D3
D3
11
D2
D2
12
D1
D1
13
D0
D0
14
WAKE
CS
S1
S1
15
), before
) speci-
S0
S0
16
11