ispLSI 1016-90LJ Lattice, ispLSI 1016-90LJ Datasheet
ispLSI 1016-90LJ
Specifications of ispLSI 1016-90LJ
Related parts for ispLSI 1016-90LJ
ispLSI 1016-90LJ Summary of contents
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... The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number ispLSI 1016-60LJ ispLSI 1016-80LJ ispLSI 1016-90LJ ispLSI 1016-110LJ ispLSI 1016-60LJI ispLSI 1016 ispLSI 1016-60LT44 ispLSI 1016-80LT44 ...
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... The basic unit of logic on the ispLSI 1016 device is the Generic Logic Block (GLB). The GLBs are labeled A0 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016 device ...
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... CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device ...
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... A SYMBOL PARAMETER C 1 Dedicated Input Capacitance C I/O and Clock Capacitance Guaranteed but not 100% tested. Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1016 1 +1.0V CC +1.0V CC Commercial T = 0°C to +70°C A Industrial T = -40°C to +85°C A Military/883 T = -55°C to +125°C ...
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... Refer to the Power Consumption sec- CC tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1016 Figure 2. Test Load GND to 3.0V ≤ 3ns 10% to 90% 1.5V 1.5V ...
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... Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions Section. Specifications ispLSI 1016 Over Recommended Operating Conditions 1 3 ...
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... Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions Section. Specifications ispLSI 1016 Over Recommended Operating Conditions 1 3 ...
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... ORP Bypass Delay 46 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros. Specifications ispLSI 1016 -110 -90 UNITS MIN. MAX. ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line 54 Global Reset Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1016 1 8 -110 -90 UNITS MIN. MAX. MIN. MAX. – ...
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... ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros. Specifications ispLSI 1016 -80 -60 UNITS MIN. MAX. ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset t gr Global Reset to GLB and I/O Registers 55 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1016 1 10 -80 -60 UNITS MIN. MAX. MIN. MAX. ...
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... Clock (max) + Reg co + Output ( gy0(max) + gco + ( ) ( = #50 + #40 + #52 + #40 16 (3.5 + 1.5 + 5.0) + (1.5) + (2.5 + 2.5) 1. Calculations are based upon timing specifications for the ispLSI 1016-90. Specifications ispLSI 1016 GRP GLB Feedback GRP Bypass GLB Reg Bypass #28 #33 GRP 20 PT Loading XOR Delays Delay #34, 35, 36 #27, 29, ...
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... Figure 3. Typical Device Power Consumption vs fmax 150 100 can be estimated for the ispLSI 1016 using the following equation PTs * 0.45 nets * Max. freq * 0.009) where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The I CC estimate is based on typical conditions ( ...
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... Y1/RESET 35 29 GND Pins have dual function capability. Specifications ispLSI 1016 TQFP JLCC PIN NUMBERS Input/Output Pins - These are the general purpose I/O 10, 11, 12, 15, 16, 17, 18, pins used by the logic array Dedicated input pins to the device ...
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... Pin Configuration ispLSI 1016 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I VCC ispEN 1 SDI/IN 0 I/O 0 I Pins have dual function capability. ispLSI 1016 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I VCC ispEN 1 SDI/IN 0 I/O 0 I Pins have dual function capability. Specifications ispLSI 1016 ...
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... Pin Configuration ispLSI 1016 44-Pin JLCC Pinout Diagram I/O 28 I/O 29 I VCC ispEN 1 SDI/IN 0 I/O 0 I Pins have dual function capability. Specifications ispLSI 1016 ispLSI 1016/883 34 12 Top View ...
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... Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. Specifications ispLSI 1016 — 1016 XXX X XXX X ispLSI COMMERCIAL t Ordering Number pd (ns) 10 ispLSI 1016-110LJ 12 ispLSI 1016-90LJ 12 ispLSI 1016-90LT44 15 ispLSI 1016-80LJ 15 ispLSI 1016-80LT44 20 ispLSI 1016-60LJ 20 ispLSI 1016-60LT44 INDUSTRIAL t Ordering Number pd (ns) ...