ispLSI 1048-50LQ Lattice, ispLSI 1048-50LQ Datasheet - Page 10

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ispLSI 1048-50LQ

Manufacturer Part Number
ispLSI 1048-50LQ
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
Power consumption in the ispLSI 1048 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
Maximum GRP Delay vs GLB Loads
Power Consumption
I CC can be estimated for the ispLSI 1048 using the following equation:
I CC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I CC estimate is based on typical conditions (V CC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the
program in the device, the actual I CC should be verified.
8
7
6
5
4
3
2
1
0
4
250
200
150
100
50
0
Notes: Configuration of Twelve 16-bit Counters
GLB Loads
10
8
Typical Current at 5V, 25¡C
20
ispLSI 1048
30
9
12
f
max (MHz)
ure 3 shows the relationship between power and operat-
ing speed.
40
Specifications ispLSI 1048
50
16
60
ispLSI 1048-50
ispLSI 1048-70
ispLSI 1048-80
70
80
0126A-48-80-isp
0127A-48-80-isp

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