ispLSI 2064A-100LTN100 Lattice, ispLSI 2064A-100LTN100 Datasheet - Page 2

• Manufacturer Part Number: ispLSI 2064A-100LTN100
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 2064A-100LTN100

• Rohs: yes
• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 111 MHz
• Delay Time: 13 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 175 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

Figure 1. ispLSI 2064/A Functional Block Diagram
The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each ispLSI
2064 and 2064A device contains two Megablocks.
Functional Block Diagram
MODE/IN 1
SDI/IN 0
RESET
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
Megablock
A1
A2
A3
A0
A4
Output Routing Pool (ORP)
B7
A5
Global Routing Pool
Input Bus
Output Routing Pool (ORP)
(GRP)
B6
2
A6
Input Bus
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064 and 2064A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Specifications ispLSI 2064/A
B5
A7
B4
B2
B0
B3
B1
Blocks (GLBs)
Generic Logic
0139B(1)isp/2064
SCLK/IN 3
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
SDO/IN 2