ispLSI 1032E-100LTN Lattice, ispLSI 1032E-100LTN Datasheet
ispLSI 1032E-100LTN
Specifications of ispLSI 1032E-100LTN
Related parts for ispLSI 1032E-100LTN
ispLSI 1032E-100LTN Summary of contents
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... N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued Phone (503) 268-8000 Internet: http://www.latticesemi.com Reference PCN PCN#13-10 PCN#05A-10 FAX (503) 268-8347 ...
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... Optimized Global Routing Pool Provides Global Interconnectivity Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 1032 Functional Block Diagram RESET Generic Logic Blocks (GLBs) I I/O 1 I I I I/O 9 ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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... Typical values are and Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec- CC tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1032 Figure 2. Test Load GND to 3.0V ≤ ...
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External Timing Parameters 5 2 TEST PARAMETER # DESCRIPTION COND. t pd1 A 1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t iobp 20 I/O Register Bypass t iolat 21 I/O Latch Delay t iosu I/O Register Setup Time before Clock 22 t I/O Register Hold Time after Clock ioh 23 t ioco ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs t ob Output Buffer Delay 47 t I/O Cell OE to Output Enabled oen 48 t odis 49 I/O Cell OE to Output Disabled Clocks t gy0 Clock Delay Global ...
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Timing Model I/O Cell Ded. In #26 I/O Reg Bypass I/O Pin #20 (Input) Input Register Q D RST #55 # 30, 31, 32 Reset Y1,2 Derivations of su, h and co ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1032 device depends on two primary factors: the speed at which the device is operating, and the number of Product ...
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Pin Description Name PLCC Pin Numbers I I/O 3 26, 27, I I/O 7 30, 31, I I/O 11 34, 35, I I/O 15 38, 39, I I/O 19 45, ...
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Pin Description Name TQFP Pin Numbers I I/O 3 17, 18, I I/O 7 21, 22, I I/O 11 29, 30, I I/O 15 33, 34, I I/O 19 40, ...
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Pin Description Name CPGA Pin Numbers I I/O 3 F1, H1, I I/O 7 K1, J2, I I/O 11 K3, L2, I I/O 15 L4, J5, I I/O 19 L7, ...
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Pin Configuration ispLSI 1032 84-Pin PLCC Pinout Diagram I/O 60 ...
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Pin Configuration ispLSI 1032 100-pin TQFP Pinout Diagram ...
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Pin Configuration ispLSI 1032/883 84-Pin CPGA Pinout Diagram I/O38 I/O41 I/O42 I/O36 I/O39 I/O40 I/O35 I/O37 I/O33 I/O34 Y1 IN4 I/O32 Vcc I/O31 GND *SCLK IN3 I/O30 I/O29 I/O28 I/O26 I/O27 I/O25 I/O23 I/O24 I/O22 ...
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... Ordering Information f Family ispLSI f Family ispLSI f Family max (MHz) ispLSI 60 Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. Specifications ispLSI 1032 — 1032 COMMERCIAL t Ordering Number max (MHz) pd (ns) ...