ispLSI 2064A-125LJN84 Lattice, ispLSI 2064A-125LJN84 Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
ispLSI 2064A-125LJN84
Manufacturer Part Number
ispLSI 2064A-125LJN84
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.ISPLSI_2064A-125LJ84.pdf
(14 pages)
Specifications of ispLSI 2064A-125LJN84
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
125 MHz
Delay Time
10 ns
Number Of Programmable I/os
64
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-84
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
175 mA
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Internal Timing Parameters
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
PARAMETER
ORP
Outputs
Inputs
Clocks
Global Reset
t
t
GRP
t
GLB
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
io
din
grp
4ptbp
4ptbp
1ptxor
20ptxor
xoradj
gbp
gsu
gh
gco
gro
ptre
ptoe
ptck
orp
orpbp
ob
sl
oen
odis
goe
gy0
gy1/2
gr
45
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
#
2
Input Buffer Delay
Dedicated Input Delay
GRP Delay
4 Product Term Bypass Comb. Path Delay
4 Product Term Bypass Reg. Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
Output Buffer Delay
Output Slew Limited Delay Adder
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Global Output Enable
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Global Reset to GLB
DESCRIPTION
Over Recommended Operating Conditions
1
3
6
Specifications ispLSI 2064/A
MIN. MAX.
0.8
3.0
3.3
2.3
2.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-125
10.0
0.2
1.5
1.3
4.5
5.0
5.7
6.0
6.5
0.5
0.2
1.1
4.8
7.3
5.6
0.8
0.3
1.2
3.2
3.2
3.8
2.3
2.3
6.9
–
–
MIN.
1.2
4.0
4.1
2.7
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-100
MAX.
10.0
0.5
2.2
1.7
5.8
5.8
6.8
7.3
8.0
0.5
0.3
1.3
6.1
8.6
7.1
1.4
0.4
1.6
4.2
4.2
4.8
2.7
2.7
9.2
–
–
MIN. MAX.
1.4
6.0
5.6
3.6
3.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 2- 0036C/2064-130
-80
10.2
10.0
11.4
1.8
4.4
2.6
8.1
6.8
8.0
8.8
9.8
1.3
0.4
1.6
8.6
9.0
2.0
0.5
2.0
4.6
4.6
7.4
3.6
3.6
–
–
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns