LCMXO640E-4FN256C Lattice, LCMXO640E-4FN256C Datasheet - Page 8
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LCMXO640E-4FN256C
Manufacturer Part Number
LCMXO640E-4FN256C
Description
CPLD - Complex Programmable Logic Devices Use LCMXO640E-4FTN25
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-5TN100C.pdf
(96 pages)
Specifications of LCMXO640E-4FN256C
Rohs
yes
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
550 MHz
Delay Time
4.2 ns
Number Of Programmable I/os
159
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
14 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640E-4FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A
LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by program-
ming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger
lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the
software will construct these using distributed memory primitives that represent the capabilities of the PFU.
Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows
the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice
functions as the read-write port, while the other companion Slice supports the read-only port. For more information
on RAM mode in MachXO devices, please see details of additional technical documentation at the end of this data
sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Ripple mode multiplier building block
• Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
PFU Slice
PFF Slice
LUT 4x2 or LUT 5x1
LUT 4x2 or LUT 5x1
Number of Slices
Note: SPR = Single Port RAM, DPR = Dual Port RAM
Logic
2-bit Arithmetic Unit
2-bit Arithmetic Unit
2-5
Ripple
SPR16x2
1
DPR16x2
2
SP 16x2
RAM
N/A
MachXO Family Data Sheet
ROM 16x1 x 2
ROM 16x1 x 2
ROM
Architecture