MAX174BEWI-T Maxim Integrated, MAX174BEWI-T Datasheet - Page 10

• Manufacturer Part Number: MAX174BEWI-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX174BEWI-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 125 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-28 Wide
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 10 V

R/C must be low before asserting both CE and CS. If it
is high, a brief read operation occurs possibly resulting
in system bus contention. To initiate a conversion, use
either CE or CS. CE is recommended since it is shorter
by one propagation delay than CS and is the faster input
of the two. CE is used to begin the conversion in
The STS output is high during the conversion indicating
the ADC is busy. During this period, additional convert
start commands will be ignored, so that the conversion
Figure 4. Convert Start Timing
D0–D11
STS
R/C
CE
CS
A0
Convert Start Timing—Full Control Mode
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t
t
SSC
SRC
t
SAC
Industry-Standard, Complete 12-Bit ADCs
HIGH IMPEDANCE
t
t
t
t
HSC
HRC
HAC
DSC
t
HEC
Timing and Control
t
C
Figure
4.
MAX174/MX574A/MX674A
cannot be prematurely terminated or restarted. However,
if the state of A0 is changed after the beginning of the
conversion, any additional start conversion transitions
will latch the new state of A0, possibly resulting in an
incorrect conversion length (8 bits vs. 12 bits) for that
conversion.
Figure 5
data, access time is measured from when CE and R/C
are both high. Access time is extended 10ns if CS is used
to initiate a read.
Figure 5. Read Timing
D0–D11
STS
R/C
CS
CE
A0
illustrates the read-cycle timing. While reading
Read Timing—Full Control Mode
HIGH IMPEDANCE
t
t
SAR
SRR
t
SSR
t
DD
t
t
t
HSR
HRR
HAR
t
HD,
t
HL