MAX1444EHJ/V+T Maxim Integrated, MAX1444EHJ/V+T Datasheet - Page 5

• Manufacturer Part Number: MAX1444EHJ/V+T
• Description: Analog to Digital Converters - ADC 10-Bit 40Msps 3.0V Low-Power ADC with Internal Reference
• Manufacturer: Maxim Integrated

Specifications of MAX1444EHJ/V+T

• Number Of Channels: 1
• Architecture: Pipeline
• Conversion Rate: 40 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: 59.5 dB
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Power Dissipation: 1495.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.024 V

ELECTRICAL CHARACTERISTICS (continued)
(V
REFIN through a 10kΩ resistor; V
to T
cal values are at T
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
Note 3: Digital outputs settle to V
Note 4: REFIN is driven externally. REFP, COM, and REFN are left open while powered down.
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE Fall to Output Enable
OE Rise to Output Disable
CLK Pulse Width High
CLK Pulse Width Low
Wake-up Time
DD
MAX
= 3V; OV
, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typi-
input voltage range.
6dB better if referenced to the two-tone envelope.
PARAMETER
DD
A
= 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; V
= +25°C.)
_______________________________________________________________________________________
IN
IH
= 2V
, V
SYMBOL
t
t
DISABLE
ENABLE
IL
V
I
t
OV
PSRR
I
C
I
OVDD
WAKE
V
LEAK
V
V
HYST
C
VDD
t
t
.
t
I
P-P
I
OUT
DO
CH
CL
OH
IH
OL
DD
IL
IN
DD
10-Bit, 40Msps, 3.0V, Low-Power
(differential with respect to COM); C
V
V
I
I
OE = OV
OE = OV
O p er ati ng , f
S hutd ow n, cl ock i d l e, P D = O E = OV
O p er ati ng , f
S hutd ow n, cl ock i d l e, P D = O E = OV
Offset
Gain
Figure 6 (Note 3)
Figure 5
Figure 5
Figure 6, clock period 25ns
Figure 6, clock period 25ns
(Note 4)
SINK
SOURCE
IH
IL
= 0V
= V
ADC with Internal Reference
= 200μA
DD
DD
DD
= 200μA
= OV
I N
I N
CONDITIONS
= 19.91M H z at - 0.5d BFS
= 19.91M H z at - 0.5d BFS
DD
L
= 10pF at digital outputs; f
D D
D D
OV
MIN
0.2
2.7
1.7
REFIN
DD
-
= 2.048V; REFOUT connected to
12.5 ±3.8
12.5 ±3.8
TYP
±0.1
±0.1
0.1
3.0
3.0
4.5
1.7
19
10
15
5
5
4
1
5
CLK
= 40MHz; T
MAX
±10
0.2
3.6
3.6
±5
±5
27
15
20
8
A
UNITS
mV/V
%/V
mA
mA
= T
µA
pF
µA
pF
µA
µA
ns
ns
ns
ns
ns
µs
V
V
V
V
V
MIN
5