MAX1111EEE-T Maxim Integrated, MAX1111EEE-T Datasheet - Page 14

• Manufacturer Part Number: MAX1111EEE-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1111EEE-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.048 V or External

Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz. SSTRB goes
low at the start of the conversion and then goes high
when the conversion is complete. SSTRB is low for
25µs (typ), during which time SCLK should remain low
for best noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the second falling clock edge produces the
MSB of the conversion at DOUT, followed by the
+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
Figure 10. Internal Clock Mode Timing
Figure 11. Internal Clock Mode SSTRB Detailed Timing
14
______________________________________________________________________________________
SSTRB
DOUT
A/D STATE
SSTRB
SCLK
SCLK
DIN
CS
CS
START
1
IDLE
SEL2 SEL1 SEL0 UNI/
PD0 CLOCK IN
2
3
4
t
CSH
BIP
5
SGL/
4µs (f
DIF
6
SCLK
PD1
t
Internal Clock
7
ACQ
t
SSTRB
= 500kHz)
PD0
8
CONVERSION
25µs TYP
t
CONV
t
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CONV
9
remaining bits in MSB-first format (Figure 10). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1110/MAX1111 and three-states DOUT, but it
does not adversely affect an internal clock-mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 11 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1110/MAX1111 at clock rates up to 2MHz, pro-
vided that the minimum acquisition time, t
above 1µs.
10
B7
11
B6
12
t
SCK
15
16
B1
17
B0
18
FILLED WITH
ZEROS
t
CSS
ACQ
IDLE
, is kept