MAX1072ETC Maxim Integrated, MAX1072ETC Datasheet - Page 14

• Manufacturer Part Number: MAX1072ETC
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1072ETC

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.8 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: 60 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

For continuous conversion, set the serial port to trans-
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without CPU intervention. Connect the V
pin to the TMS320C54_ supply voltage when the
MAX1072/MAX1075 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
Another method of connecting the MAX1072/MAX1075
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16 where serial clock (CLOCK) drives the CLKR
and SCLK and the convert signal (CONVERT) drives
the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
14
______________________________________________________________________________________
MAX1072
MAX1075
CNVST
DOUT
SCLK
V
L
DV
CLKX
CLKR
FSX
FSR
DR
DD
TMS320C54_
L
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
intervention. Connect the V
supply voltage when the MAX1072/MAX1075 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
The MAX1072/MAX1075 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
The MAX1072/MAX1075 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1072/MAX1075 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1072/MAX1075. For continuous conver-
sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
Figure 16. Interfacing to the TMS320C54_ External Clocks
MAX1072
MAX1075
CONVERT
DSP Interface to the ADSP21_ _ _
CLOCK
CNVST
DOUT
SCLK
V
L
L
pin to the TMS320C54_
DV
CLKR
FSR
DR
DD
TMS320C54_